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a s 3 5 4 3 h i g h e n d ste r e o a ud i o c o d e c w i th s y s t e m p m u www.austriamicrosystems.com r evision 1.11 1 - 91 data sheet 1 general description the AS3543 is an ultra low power stereo audio codec a nd is designed for portable digital audio applications. it allows high-end quality playback with up to 100dba snr and recording in fm quality. with one microphone (including pre-amplifier and supply for an electret micro- phone) and two line inputs, it allows connecting a variety of audio inputs. the different audio signals can be mixed via a 6-channel mixer and fed to either a headphone out- put for 16 /32 headsets or a line output. both outputs have a ground noise cancellation to use it e.g. in car docking stations. the audio outputs have also an auto fading implemented which performs the fade-in, fade- out as well as the transition between specific volume levels automatically with an selectable timing. further the device offers advanced power management functions. all necessary ics and peripherals in a digital audio player are supplied by the AS3543. it features 2 dcdc converters for core and memory/periphery supply as well as 4 ldos. both dcdc converter feature dvm (dynamic voltage management) with an selectable tim- ing for the voltage stepping. the different regulated sup- ply voltages are programmable via the serial control interface. the step-up converter for the backlight can operate up to 15v (with an external transistor even higher) in volt- age and current control mode. an internal voltage pro- tection is limiting the output voltage in the case of external component failures. 2 high voltage current sinks can be used to operate two, if needed also unbalanced, led strings. an automatic dimming function allows a logarithmic on/off of the backlight with selectable timing. AS3543 also contains a li-ion battery charger with con- stant current, constant voltage and trickle charging. the maximum charging current is 460ma. an integrated bat- tery switch is separating the battery during charging or whenever an external power supply is present. with this switch it is also possible to operate with no or deeply dis- charged batteries. the AS3543 has an on-chip, phase locked loop (pll) which generates the needed internal codec master clock. i2s frame and shift-clock have to be applied from the processor for playback and recording. further the AS3543 has an independent 32khz real time clock (rtc) on chip which allows a complete power down of the system cpu while only consuming less than 1a. an internal switch automatically switches between the rtc backup-battery and main battery supply. the single supply voltage may vary from 2.7v to 5.5v. 2 key features audio audio power consumption: - 5mw: 96db dac to headphone @ 1.8v, 32 - 7mw: 100db dac to headphone @ 2.9v, 32 sigma delta converters dac - 98db snr ('a' weighted) @ 1.7v - 102db snr ('a' weighted) @ 2.9v adc - 85db snr ('a' weighted) @ 1.7v sampling frequency - dac: 8-96khz - adc: 8-24khz high efficiency headphone amplifier volume control via serial interface 32 steps @1.5db and mute 2x12mw @16 driver capability@ 1.8v supply thd -74db @16 ; 1.8v 2x40mw @16 driver capability@ 3.6v supply thd -77db @16 ; 3.6v headphone and over-current detection phantom ground eliminates large capacitors ground noise cancellation line output volume control via serial interface 32 steps @1.5db and mute 0.6vp @10k , 1.8v ground noise cancellation ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 2 - 91 AS3543 3v2 data sheet - a p p l i c a t i o n s microphone input 3 gain pre-setting (30db/36db/42db) and agc 32 gain steps @1.5db and mute supply for electret microphone microphone detection remote control by switch 2 line inputs volume control via serial interface 32 steps @1.5db and mute stereo or 2x mono audio mixer 8 channel input/output mixer with agc mixes line inputs, microphone and adc with dac left and right channels independent power management voltage generation step down for cpu core (0.61v-3.35v, 250ma) step down for peripheral (0.61v-3.35v, 250ma) ldo1 for afe supply (1.7v (1.65-3.2v), 50ma) ldo2 for afe supply (2.7v (2.3-3.5v), 200ma) ldo3 for peripherals (1.2v-3.5v, 100/200ma) ldo4 for peripherals (1.2v-3.5v, 100/200ma) vbus comparator separate input for ldo3 power supply supervision & hibernation modes 5sec and 10sec emergency shut-down backlight driver step up for backlight (15v (25v)) current control mode (1.2-37.2ma) voltage control mode 2 hv current sinks automatic dimming over-voltage protection battery charger automatic trickle charge (55ma) prog. constant current charging (55-460ma) prog. constant voltage charging (3.9v-4.25v) current limitation for usb mode integrated battery switch general supervisor automatic battery monitoring with interrupt genera- t ion and selectable warning level automatic temperature monitoring with interrupt g eneration and selectable warning and shutdown levels real time clock ultra low power 32khz oscillator 32bit rtc sec counter, 96 days auto wake-up selectable interrupt (seconds or minutes) 128bit free sram for random settings 32khz clock output to peripheral voltage generation trim able oscillator <1ua total power consumption auxiliary oscillator (system clock generation) low power 12-24mhz oscillator clock output general purpose adc 10bit resolution 22 inputs analog multiplexer interfaces 2 wire serial control interface reset pin with selectable delay, power good pin 64bit unique id (otp) 26 different interrupts package ctbga68 [6.0x6.0x1.1mm] 0.5mm pitch 3 applications portable digital audio/video player and recorder pd a, smartphone ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 3 - 91 AS3543 3v2 data sheet - a p p l i c a t i o n s figure 1. block diagram ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 4 - 91 AS3543 3v2 data sheet - a p p l i c a t i o n s contents 1 general description ............................................................................................................................ 1 2 key features .......................................................................................................................................1 3 applications ........................................................................................................................................ 2 4 pinout ................................................................................................................................................... 6 4.1 pin assingment . .............................................................................................................................................6 4.2 pin description ...............................................................................................................................................6 5 absolute maximum ratings ............................................................................................................... 9 6 electrical characteristics ................................................................................................................. 11 7 typical operating characteristics ................................................................................................... 13 8 detailed description - audio functions .......................................................................................... 14 8.1 audio line inputs (2x) . .................................................................................................................................14 8.2 microphone input .........................................................................................................................................15 8.3 line output ..................................................................................................................................................17 8.4 headphone output .......................................................................................................................................18 8.5 dac, adc and i2s digital audio interface ..................................................................................................21 8.6 audio output mixer ......................................................................................................................................24 8.7 2-wire-serial control interface ....................................................................................................................25 9 detailed description - power management functions .................................................................. 28 9.1 low drop out regulators . ...........................................................................................................................28 9.2 dcdc step-down converter (2x) ................................................................................................................31 9.3 15v step-up dcdc converter ....................................................................................................................35 9.4 charger ........................................................................................................................................................37 9.5 battery switch ..............................................................................................................................................40 10 detailed description - system functions ................................................................................... 41 10.1 system . ...................................................................................................................................................41 10.2 hibernation ................................................................................................................................................43 10.3 supervisor ..................................................................................................................................................44 10.4 interrupt generation ...................................................................................................................................44 10.5 real time clock .........................................................................................................................................46 10.6 10-bit adc .................................................................................................................................................47 10.7 gpio pins ..................................................................................................................................................48 10.8 12-24mhz oscillator ..................................................................................................................................49 10.9 unique id code (64 bit otp rom) ...........................................................................................................50 11 register definition .......................................................................................................................... 51 1 2 application information .................................................................................................................. 88 13 package drawings and markings .................................................................................................. 89 14 ordering information ...................................................................................................................... 90 ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 5 - 91 AS3543 3v2 data sheet - a p p l i c a t i o n s revision history table 1. revision history revision date owner description 1.01 17.4.2009 pkm official release 1.10 5.2009 pkm added audio characterisation data 1.11 12.2012 pkm typo and register bit description corrections ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 6 - 91 AS3543 3v2 data sheet - p i n o u t 4 pinout 4.1 pin assignment figure 2. pin assignments (top view) 4.2 pin description table 2. pin description for AS3543 pin number pin name type description k2 xin24m ana io 24mhz crystal input (ext. 22pf c needed) k3 xout24m ana io 24mhz crystal output (ext. 22pf c needed) j2 pwrup dig in power up input g2 fvdd sup in digital pos. supply (e.g. dac, ) j3 xres dig out reset output j4 xirq dig out interrupt request output j5 pwgd dig io powerup sequence complete output e4 mclk dig in mclk input f4 sclk dig in i2s shift clock input g4 lrck dig in i2s frame clock input g5 sdi dig in i2s data input to dac 1 2 3 4 5 6 7 8 9 10 a chgout bvddbsw pvdd1 pvdd2 hpcm hpr hpvss hpl b c hgin battemp bvddp1 bvdd vdd17in hpgnd hpvdd lognd loutr loutl c v ss15v sw15v lin1r lin1l d is ink2 vss vbus lin2r lin2l mics e bvddc2 isink1 mclk vprog3 micn micp f l xc2 cvdd2 sclk vprog2 agnd avss g f vdd lrck sdi sdo vprog1 vref h cvss12 cvdd1 avdd27 avdd17 j l xc1 pwrup xres xirq pwgd q24m q32k cscl rvdd xin32k k bvddc1 xin24m xout24m d vss dvdd csda bvddr xout32k ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 7 - 91 AS3543 3v2 data sheet - p i n o u t k5 dvss gnd d igital circuit neg. supply terminal k6 dvdd sup in digital periphery pos. supply g6 sdo dig out i2s data output from adc j6 q24m dig io 24mhz clock digital output j7 q32k dig io 32khz clock digital output j8 cscl dig in 2 wire serif clock input k8 csda dig io 2 wire serif data i/o k9 bvddr sup in secondary rtc supply - supercap k10 xout32k ana io 32khz crystal output xin j10 xin32k ana io 32khz crystal input xout j9 rvdd ana io rtc ldo output, rtc supply input g9 vref ana io dac reference pin g7 vprg1 ana in core supply voltage definition pin f7 vprg2 ana in memory supply voltage definition pin e7 vprg3 ana in powerup sequence definition pin f10 avss gnd ground (analog) f9 agnd ana io analog common mode voltage pin e10 micp ana in microphone input p e9 micn ana in microphone input n d9 mics ana io microphone supply output / remote control input d6 lin2r ana in analog line input 2 right channel d7 lin2l ana in analog line input 2 left channel b8 lognd ana io line output common mode voltage pin c9 lin1r ana io analog line input 1 right channel b9 loutr ana out analog line output right channel b10 loutl ana out analog line output left channel c10 lin1l ana io analog line input 1 right channel b7 hpvdd sup in headphone supply default 1.8v (max. 3.6v) a10 hpl ana out headphone output left channel a8 hpr ana out headphone output right channel a6 hpcm ana out headphone common mode buffer pin a9 hpvss gnd headphone ground b6 hpgnd ana io headphone common mode voltage pin h10 avdd17 sup io ldo1 output default 1.7v b5 vdd17in sup in ldo1 pos. supply terminal h9 avdd27 sup io ldo2 output default 2.7v b4 bvdd sup in main battery supply input (2.7-5.5v) d5 vbus ana in vbus detection input a5 pvdd2 ana out ldo4 output (pvdd2) a3 pvdd1 ana out ldo3 output (pvdd1) table 2. pin description for AS3543 pin number pin name type description ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 8 - 91 AS3543 3v2 data sheet - p i n o u t b3 bvddp1 sup in l do3 pos. supply terminal a2 bvddbsw sup io battery switch output to be connected against bvdd a1 chgout sup io li-ion charger output (battery switch input) b1 chgin sup in li-ion charger input b2 battemp ana io li-ion charger battery temp. sensor input d4 vss gnd power management neg. reference supply c1 vss15v gnd dcdc15v & current sinks neg. supply terminal c2 sw15v dig out dcdc15v switch output to coil d2 isink2 ana io dcdc15v load current sink2 terminal e2 isink1 ana io dcdc15v load current sink1 terminal e1 bvddc2 sup in cvdd2 step down pos. supply terminal f1 lxc2 dig out cvdd2 step down switch output to coil f2 cvdd2 ana in cvdd2 and feedback pin h1 cvss12 gnd dcdc12 substrate pin h2 cvdd1 ana in cvdd1 and feedback pin j1 lxc1 dig out cvdd1 step down switch output to coil k1 bvddc1 sup in cvdd1 step down pos. supply terminal table 2. pin description for AS3543 pin number pin name type description ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 9 - 91 AS3543 3v2 data sheet - a b s o l u t e m a x i m u m r a t i n g s 5 absolute maximum ratings stresses beyond those listed in t able 3 may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in electrical character- is tics on page 11 is not implied. exposure to absolute maximum rating c onditions for extended periods may affect device reliability. the device should be operated under recommended operating conditions. table 3. absolute maximum ratings parameter min max units comments 5v pins - 0.5 7.0 v applicable for pins bvdd, bvddc1, bvddc2, bvddr, bvddp1, bvddbsw, chgin, chgout, vbus, cscl, csda, pwrup 3v pins -0.5 5.0 v applicable for pins dvdd, hpvdd, fvdd, vdd17in, rvdd, vprg1, vprg2, vprg3 15v pins -0.5 17 v applicable for pin sw15v, isink1/2 voltage difference at vss terminals -0.5 0.5 v applicable for pins vss, vss15v, cvss12, hpvss, avss, dvss 3.3v pins with protection to avdd27 -0.5 5.0 avdd27 v applicable for pins battemp, hpgnd 3.3v pins with protection to dvdd -0.5 5.0 dvdd+0.5 v applicable for pins mclk, lrck, sclk, sdi, sdo, xirq, xres, pwgd, q32k, q24m, xin24m, xout24m 3.3v pins with protection to rvdd -0.5 5.0 rvdd+0.5 v applicable for pins xin32k, xout32k 3.3v pins with protection to avdd17 -0.5 5.0 avdd17+0.5 v applicable for pins loutl/r, lognd, vref, agnd, lin1l/r, lin2l/r, micp/ n,mics 3.3v pins with protection to hpvdd -0.5 5.0 hpvdd+0.5 v applicable for pins hpcm, hpr/l voltage regulator pins with protection to bvdd -0.5 5.0 bvdd+0.5 v applicable for pins avdd27, pvdd1/2, cvdd1, lxc1, cvdd2, lxc2 voltage regulator pins with protection to avdd17in -0.5 5.0 avdd17in +0.5 v applicable for pins avdd17 input current (latch-up immunity) -100 100 ma norm: jedec 17 continuous power dissipation (t a = +70oc) continuous power dissipation 5 00 mw p t 1 for ctbga68 package electrostatic discharge electrostatic discharge hbm + /-1 kv norm: jedec jesd22-a114c temperature ranges and storage conditions operating temperature range -20 +85 oc j unction temperature +110 oc storage temperature range -50 +125 oc humidity non-condensing 5 85 % ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 10 - 91 AS3543 3v2 data sheet - a b s o l u t e m a x i m u m r a t i n g s bump temperature (soldering) package body temperature 2 60 c norm ipc/jedec j-std-020c, reflects moisture sensitivity level only solder profile 235 245 c peak temperature 30 45 s well time above 217 c moisture sensitive level 3 1 represents a max. floor live time of 168h 1. depending on actual pcb layout and pcb used table 3. absolute maximum ratings parameter min max units comments ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 11 - 91 AS3543 3v2 data sheet - e l e c t r i c a l c h a r a c t e r i s t i c s 6 electrical characteristics bvdd=+2.7v...+5.5v, t a =-20oc...+85oc. typical values are at bvdd=+3.6v, t a =+25oc, unless otherwise specified. t able 4. electrical characteristics symbol parameter condition min typ max unit supply voltages bvddx b attery supply voltage bvdd, bvddbsw, bvddc1, bvddc2, bvddp1 2.7 3.6 5.5 v bvddr rtc secondary supply voltage 1.2 5.5 v vbus usb vbus voltage 5.0 5.5 v chgin charger supply voltage 4.5 5.5 v hpvdd hp supply voltage 1.8 3.6 v dvdd digital periphery supply voltage 1.8 2.9 3.6 v vdd17in ldo1 input voltage 1.8 3.6 v fvdd digital supply voltage 1.75 1.8 3.5 v avdd27 analogue supply voltage 2.6 2.7 3.5 v avdd17 analogue supply voltage 1.7 1.7 3.5 v agnd analog ground voltage internally generated avdd17 /2 v v delta - d ifference of negative supplies cvss12, vss15v, hpvss, avss, dvss, vss to achieve good performance, the negative supply terminals should be connected to low impedance ground plane. -0.1 0.1 v v delta + d ifference of positive supplies rvdd-avdd27; avdd17-avdd27; fvdd-avdd27 0 v avdd27-hpvdd 0.3 v bvdd-avdd27 0.1 v por & watchdog v por_on power-on reset activation l evel power-on reset activation level when dvdd decreases 2.15 v v por_off power-on reset release l evel power-on reset release when dvdd increases 2.0 v v por_hy power-on hysteresis 1 00 mv f lrclk_wd lrclk watchdog 2 4.1 8 khz pwrup t on_delay delay time of pin pwrup minimum key press time 3 0 ms v pwrup_l input level low, pi n pwrup, bvdd>3v 0.5 v v pwrup_h input level high pi n pwrup, bvdd>3v bvdd/ 3 v pin pwrup, bvdd<=3v 1 v i pwrup internal pull-down current so urce pin pwrup; @2.9v 2.5 7 19 ua ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 12 - 91 AS3543 3v2 data sheet - e l e c t r i c a l c h a r a c t e r i s t i c s digital inputs/outputs v do_dl digital output driver c apability (drive low) pins xres, xirq, pwgd @ 8ma, sdo 10% dvdd v v do_dh digital output driver c apability (drive high) pins xres, xirq @ 8ma, push/pull mode only, sdo 90% dvdd v i pu internal pull-up current so urce pins xres, xirq, pwgd, q32k, q24m; @0v 10 a v di_l digital input level low pin sdi, sclk, mclk, lrck 3 0% dvdd v v di_h digital input level high pin sdi, sclk, mclk, lrck 7 0% dvdd v f clk audio clock frequency l rck according to streamed audio data 8 96 khz block power requirements i ref reference supply current all blocks off, only ldo2 on 3 30 ua i bias audio bias current 3 2 ua i sum summing stage current 1 74 ua i lin line input stage current n o signal 146 ua i mic mic input stage current n o signal 643 ua i mics mic supply stage current n o load 201 ua i lout line output stage current n o load 436 ua i dac_gs dac gain stage current n o signal 214 ua i adc_gs adc gain stage current n o signal 1,36 ma i hph headphone stage current 1 .8v, no load 1,94 ma bias reduction on, no load 1,48 cm buffer off, no load 1,47 bias reduction on, cm buffer off, no load 0,94 i dac dac supply current l rck=48khz 1,48 ma lrck=44.1khz 1,41 lrck=32khz 1,19 lrck=16khz 0,91 lrck=8khz 0,76 i adc adc supply current l rck=24khz 1,7 ma lrck=22.05khz 1,69 lrck=16khz 1,64 lrck=8khz 1,58 lrck=4khz 1,55 i dac->hp dac playback current no load, 44.1khz, including pmu m a i line->hp line input playback current no load, including pmu m a i rtc rtc supply current 6 00 na table 4. electrical characteristics (continued) symbol parameter condition min typ max unit ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 13 - 91 AS3543 3v2 data sheet - e l e c t r i c a l c h a r a c t e r i s t i c s 6.1 audio specification bvdd=+3.6v, vdd27=hpvdd=fvdd=+3v, vdd17=+2.9v, f s =48khz, t a =+25oc, unless otherwise specified. t able 5. electrical characteristics symbol parameter condition min typ max unit dac input to line output fs full scale output r l = 10k w , f=1khz, 1v rms input 0 ,960 v rms snr signal to noise ratio a-weighted, no load, silence input 1 00 db dr dynamic range a-weighted, no load, -60db fs, f=1khz 94 db thd total harmonic distortion 1khz -1db fs input, r l =10k w - 82 db cs channel separation r l =10k w 6 2 db line input to line output fs full scale output r l = 10k w , f=1khz, 1v rms input 0 ,754 v rms snr signal to noise ratio a-weighted, no load, silence input 1 01 db thd total harmonic distortion 1khz 1v rms (-1db fs) input, r l =10k w - 72 db cs channel separation r l =10k w 1 00 db dac input to hp output fs full scale output r l =32 w 0 ,800 v rms r l =16 w 0 ,793 v rms snr signal to noise ratio a-weighted, no load, silence input 1 00 db dr dynamic range a-weighted, no load, -60db fs, f=1khz 89 db thd total harmonic distortion no load, f=1khz, -1db fs input -80 db p out =20mw, r l =32 w , f=1khz, -1db fs -79 db p out =40mw, r l =16 w , f=1khz, -1db fs -78 -60 db cs channel separation r l =32 w - 61 db r l = 16 w - 60 db line input to hp output fs full scale output r l = 32 w , f=1khz, 1v rms (fs) input 0 ,834 v rms r l = 16 w , f=1khz, 1v rms (fs) input 0 ,827 v rms snr signal to noise ratio a-weighted, no load, silence input 1 01 db thd total harmonic distortion no load, f=1khz, 1v rms -72 d b p out =20mw, r l =32 w , f=1khz, 1v rms -72 d b p out =40mw, r l =16 w , f=1khz, 1v rms -72 -60 db c s channel separation r l = 32 w 8 4 db r l = 16 w 7 2 db mic input to line output fs full scale output f=1khz, 27mv rms fs input 0 ,950 v rms snr signal to noise ratio a-weighted, no load, silence input 8 0 db thd total harmonic distortion 1khz 27mv rms fs input - 77 db mic input to adc output snr signal to noise ratio a-weighted, no load, silence input 8 1 db dr dynamic range a-weighted, no load, -60db fs, f=1khz 84 db thd total harmonic distortion 1khz 27mvv rms fs input - 65 db ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 14 - 91 AS3543 3v2 data sheet - e l e c t r i c a l c h a r a c t e r i s t i c s bvdd=+3.6v, vdd27=+2.7v, hpvdd=fvdd=1.8v, vdd17=+1.7v, f s =48khz, t a =+25oc, unless otherwise specified. t able 6. electrical characteristics symbol parameter condition min typ max unit dac input to line output fs full scale output r l = 10k w , f=1khz, 1v rms input 0 ,568 v rms snr signal to noise ratio a-weighted, no load, silence input 9 6 db dr dynamic range a-weighted, no load, -60db fs, f=1khz 95 db thd total harmonic distortion 1khz -1db fs input, r l =10k w - 90 db cs channel separation r l =10k w 6 2 db line input to line output fs full scale output r l = 10k w , f=1khz, 545mv rms input 0 ,545 v rms snr signal to noise ratio a-weighted, no load, silence input 9 7 db thd total harmonic distortion 1khz 1v rms (-1db fs) input, r l =10k w - 81 db cs channel separation r l =10k w 1 00 db dac input to hp output fs full scale output r l =32 w 0 ,560 v rms r l =16 w 0 ,550 v rms snr signal to noise ratio a-weighted, no load, silence input 9 7 db dr dynamic range a-weighted, no load, -60db fs, f=1khz 88 db thd total harmonic distortion no load, f=1khz, fs input -87 db p out =6mw, r l =32 w , f=1khz, -1db fs -81 db p out =12mw, r l =16 w , f=1khz, -1db fs -78 -60 db cs channel separation r l =32 w 6 3 db r l = 16 w 6 0 db line input to hp output fs full scale output r l = 32 w , f=1khz, 545mv rms (fs) input 0 ,450 v rms r l = 16 w , f=1khz, 545mv rms (fs) input 0 ,447 v rms snr signal to noise ratio a-weighted, no load, silence input 9 7 db thd total harmonic distortion no load, f=1khz, 545mv rms -77 d b p out =6mw, r l =32 w , f=1khz, 545mv rms -75 d b p out =12mw, r l =16 w , f=1khz, 545mv rms -75 -60 db c s channel separation r l = 32 w 7 7 db r l = 16 w 6 6 db mic input to line output fs full scale output f=1khz, 27mv rms fs input 0 ,512 v rms snr signal to noise ratio a-weighted, no load, silence input 7 5 db thd total harmonic distortion 1khz 27mv rms fs input 7 7 db mic input to adc output snr signal to noise ratio a-weighted, no load, silence input 7 7 db dr dynamic range a-weighted, no load, -60db fs, f=1khz 84 db thd total harmonic distortion 1khz 27mvv rms fs input - 64 db ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 15 - 91 AS3543 3v2 data sheet - ty p i c a l o p e r a t i n g c h a r a c t e r i s t i c s 7 typical operating characteristics bvdd = +3.6v, t a = +25oc, unless otherwise specified. ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 16 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - a u d i o f u n c t i o n s 8 detailed description - audio functions 8.1 audio line inputs (2x) 8.1.1 general the chip features two identical line inputs. the blocks can work in 2x mono single ended or in stereo single ended m ode. the volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5db each and mute. the gain can be set from C40.5db to +6db. the stage is set to mute by default. if the line input is not enabled, the volume settings are set to their default values. changing the volume and mute control can only be done after enabling the input. line input 1 and 2 are sharing one gain stage. figure 3. line inputs 8.1.2 parameter avdd17=1.7v, avdd27=2.7v, t a = 25 o c, unless otherwise mentioned t able 7. line input parameter symbol parameter condition min typ max unit v lin input signal level pl s observe gain settings. max. peak levels at any node within the circuit shall not exceed avdd avdd17 /3 avdd17 /2 v peak r lin input impedance d epending on gain setting 8-25 k ? rlin input impedance tolerance 30 % c lin input capacitance 5 pf a lin programmable gain - 40.5 +6 db gain steps discrete logarithmic gain steps 1.5 db gain step accuracy 0.25 db a linmute mute attenuation 1 00 db ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 17 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - a u d i o f u n c t i o n s 8.1.3 register description line input has to be enabled in register 14h first before other settings in register 0ah and 0bh can be programmed. 8.2 microphone input 8.2.1 general the afe offers one microphone input and one low noise microphone voltage supply (microphone bias), voice activa- t ion, microphone connect detection and push button remote control. figure 4. microphone input 8.2.2 gain stage & limiter the integrated pre-amplifier allows 3 preset gain settings. there is also a limiter which attenuates high input signals f rom e.g. electret microphones signal to 1vp. the agc has 128 steps with 0.375db with a dynamic range of the full pre-amplifier level. the agc is on by default but can be disabled by a microphone register bit. apart from the microphone pre-amplifier the microphone input signal can further be amplified with 32 @1.5db pro- grammable logarithmic gain steps and mute. all gains and mute are independently programmable. the gain can be set from C40.5db to +6db. the stage features a soft-start function. pre-amplifier and gain-stage settings can be set before enabling the micro- phone stage. after enabling the stage to gain is automatically set to the defined value by using the 128 steps of the agc. 8.2.3 supply & detection each microphone input generates a supply voltage of 1.5v above hpcm. the supply is designed for 2 ma and has a 6.5ma current limit. in off mode the mics terminal is pulled to avdd with 20kohm. a current of typically 50ua gen- erates an interrupt to inform the cpu, that a circuit is connected. when using hpcm as headset ground the hpCstage gives the interrupt. after enabling the hp-stage through the cpu the microphone detection interrupt will follow. when using the mics terminal as adc-10 input to monitor external voltages the 20kohm pull-up has to be disabled by disabling the interrupt for microphone detection. table 8. line input related register name base offset description line_in_r 2 -wire serial 0ah ri ght line input 1/2 settings, line input 2 selection line_in_l 2-wire serial 0bh le ft line input 1/2 settings audioset1 2-wire serial 14h ena ble/disable driver stage audioset3 2-wire serial 16h ena ble/disable mixer input ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 18 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - a u d i o f u n c t i o n s 8.2.4 remote control fast changes of the supply current of typically 500ua are detected as a remote button press, and an interrupt is gener- a ted. then the cpu can start the measurement of the microphone supply current with the internal 10-bit adc to distin- guish which button was pressed. as the current measurement is done via an internal resistor, only two buttons generating a current of about 0.5ma and 1ma can be detected. with this, 1ma as microphone bias is still available. 8.2.5 voice activation further a built-in voice activation comparator can actuate an interrupt if microphone input voltage of about 5mvrms is d etected. 8.2.6 parameter avdd17=1.7v, avdd27=2.7v, t a = 25 o c unless otherwise mentioned t able 9. microphone input parameter symbol parameter condition min typ max unit v micin 0 i nput signal level a micpre = 30db; amic = 0db 2 0 mv p v micin 1 a micpre = 36db; amic = 0db 1 0 mv p v micin 2 a micpre = 42db; amic = 0db 5 m v p r micin input impedance m icp, micn to agnd 7.5 k ? micin input impedance tolerance - 7 +33 % c micin input capacitance 5 pf a micpre microphone preamplifier g ain preamplifier has 3 selectable (fixed) gain settings 30 36 42 db a mic programmable gain - 40.5 +6 db gain steps discrete logarithmic gain steps 1.5 db gain step precision 0.25 db v attack limiter activation level 0 .57 v peak v decay limiter release level 0 .47 v peak a miclimit limiter gain overdrive 1 28 @ 0.375db 30 36 42 db t attack limiter attack time 5 0 s/6db t decay limiter decay time 1 20 ms/ 6db a micmute mute attenuation 1 00 db v micsup microphone supply voltage depending on v_mics setting 2 1 .55 1.26 1.06 v i micmax max. microphone supply c urrent microphones nominally need a bias current of 0.5ma-1ma 6.5 ma v noise microphone supply voltage n oise 5 v i micdet microphone detection c urrent 50 a i remdet max. remote detection c urrent 500 a ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 19 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - a u d i o f u n c t i o n s 8.2.7 register description 8.3 line output 8.3.1 general the line output is designed to provide the audio signal with a typical v peak level at a load of minimum 10k w , which is a minimum value for line inputs. if the limiters (n20/n21) are deactivated the peak output voltage is avdd17/2 vp. this afe has a combined output stage for headphone and line output with an independent gain regulation for left and right channel with 32 steps @ 1.5db each. the gain can be set from -40.5db to +6db. if the line output is not enabled, the volume settings are set to their default values. changing of volume and mute con- trol can only be done after enabling the output. figure 5. line output 8.3.2 auto fading by setting a new output volume level, the stage does a automatic fading from the current gain setting to the new target. c hanging the input multiplexer from one source to another will be done by fadeing out to mute, source changing and fading in of the new source to the target volume. change from hph-out to line-out is done by fading out of hph-out to mute and fading in of the line-out to the target volume. the fading speed can be programmed to 3 different speed levels. the immediate response can be selected as 4th state. 8.3.3 ground noise cancelation a separate ground input allows to connect a ground sense line direct from the dock connector ground or line out jack s hield to make the audio output independent from pcb ground noise. table 10. microphone input related register name base offset description mic_r 2 -wire serial 06h ri ght microphone input volume settings, agc control mic_l 2-wire serial 07h le ft microphone input volume settings, mic supply control audioset1 2-wire serial 14h ena ble/disable driver stage audioset3 2-wire serial 16h ena ble/disable mixer input irqenrd_1 2-wire serial 24h i n terrupt settings for microphone voice activation irqenrd_3 2-wire serial 26h in terrupt settings for microphone detection irqenrd_4 2-wire serial 27h in terrupt settings for remote button press detection ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 20 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - a u d i o f u n c t i o n s 8.3.4 parameter avdd17=1.7, avdd27=2.7, t a = 25 o c, unless otherwise mentioned 8.3.5 register description 8.4 headphone output the headphone output is designed to provide the audio signal with 2x40mw @ 16 w or 2x20mw @32 w , which are typ- ical values for headphones. this afe has a combined output stage for headphone and line output with an independent gain regulation for left and right channel with 32 steps @ 1.5db each. the gain can be set from -40.5db to +6db. figure 6. headphone output table 11. line output parameter symbol parameter condition min typ max unit r l_lo load impedance ( stereo mode) line inputs nominally have 10k 5 k c l_lo load capacitance ( stereo mode) 100 pf a lo programmable gain - 40.5 +6 db gain steps discrete logarithmic gain steps 1.5 db gain step accuracy 0.25 db a lomute mute attenuation 1 00 db table 12. line output related register name base offset description out_r 2 -wire serial 00h ri ght line output volume settings, mux control out_l 2-wire serial 01h le ft line output volume settings audioset2 2-wire serial 15h aut o fading timing settings audioset3 2-wire serial 16h ena ble/disable mixer input ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 21 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - a u d i o f u n c t i o n s 8.4.1 phantom ground there are 2 ways to connect a headphone to the afe. in order to spare the bulky ac/dc de-coupling capacitors at pins h pr/hpl a buffered ground (phantom ground) is provided. this common mode buffer needs to be switched on if utilized. if form factor considerations are less stringent, the headphones can be conventionally connected via 2x200f capacitors. figure 7. headphone output using common mode buffer 8.4.2 no-pop function the output is automatically set to mute when the output stage is disabled. t o avoid pop-click noise during power-up and shut-down of the headphone amplifier, a charge/discharge control of hpgnd (0v-hpvdd/2-0v) at pins hpr/hpl is incorporated into the afe. the 470nf capacitor at pin hpgnd is used to form the charge/discharge slope. pls observe that pin hpgnd is a high impedance node which must not be connected to any other external device than the 470nf buffer capacitor. to avoid pop-click noise one has to wait for 750ms in between a power-down (switch-off) and a power-up (switch-on) of the headphone amplifier. 8.4.3 auto fading by setting a new output volume level, the stage does a automatic fading from the current gain setting to the new target. c hanging the input multiplexer from one source to another will be done by fading out to mute, source changing and fading in of the new source to the target volume. change from hph-out to line-out is done by fading out of hph-out to mute and fading in of the line-out to the target volume. the fading speed can be programmed to 3 different speed levels. the immediate response can be selected as 4th state. figure 8. headphone startup with maxgain settings ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 22 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - a u d i o f u n c t i o n s figure 9. headphone change gain settings 8.4.4 headphone detection when the headphone amplifier is powered down, one can detect the connection of a headset. it only work if the headset is connected between pins hpr/hpl and hpcm. as long as the headphone amplifier is powered down, hpcm is biased to 150mv and acting as the sense pin. there is a corresponding interrupt available to be enabled. 8.4.5 over-current protection the headphone amplifier has an over-current protection (e.g. hpr/hpl is shorted). this over-current protection will power down the headphone amplifier for a programmable time-out period (512ms, 0ms). there is a corresponding interrupt available to be enabled. figure 10. headphone overcurrent off-on sequence 8.4.6 ground noise cancelation as separate ground input allows to connect a ground sense line direct from the dock connector ground or headphone jack shield to make the audio output independent from pcb ground noise. 8.4.7 power options to save power, especially when driving 32 ohm loads, a reduction of the bias current is selected. for 16ohm loads the bias current can be increased. 8.4.8 parameter avdd17=1.7, avdd27=2.7, hpvdd = 2.7v, t a = 25 o c, unless otherwise mentioned table 13. headphone output parameter symbol parameter condition min typ max unit r l_hp load impedance stereo mode 16 c l_hp load capacitance stereo mode 100 pf p hp nominal output power rl=16 , limiter enabled rl=32 , limiter enabled 40 20 mw a hp programmable gain -40.5 +6 db gain steps discrete logarithmic gain steps 1.5 db gain step accuracy 0.25 db ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 23 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - a u d i o f u n c t i o n s 8.4.9 register description 8.5 dac, adc and i2s digital audio interface 8.5.1 input the afe receives serialized audio data for the dac via pin sdi. the output of the dac is fed through a volume control to the mixer stage and to the multiplexers of line output and headphone amplifiers or direct to these output stages. this serialized audio data is a digital audio data stream with the left and the right audio channels multiplexed into one bit-stream. via pin lrck the alignment clock is input to the dac digital filters. lrck (left right clock) indicates whether the serial bit-stream received via pin sdi, represents right channel or left channel audio data. via pin sclk the bit clock for the serial bit-stream is signalled. sdi and lrck are synchronous with sclk. sdi, lrck and sclk are inputs; sdo is not used. the volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5db each. the gain can be set from C40.5db to +6db. the stage is set to mute by default. if the dac input is not enabled, the volume set- tings are set to their default values. changing the volume and mute control can only be done after enabling the input. 8.5.2 output this block consists of an audio multiplexer where the signal, which should be recorded, can be selected. the output is then fed through a volume control to the audio adc. the digital output is done via an i2s interface. the afe sends serialized audio data from the adc via pin sdo. this serialized audio data is a digital audio data stream with the left and the right audio channels multiplexed into one bit-stream. via pin lrck the alignment clock is signalled to the connected devices (e.g. cpu). lrclk (left right clock) indicates whether the serial bit-stream sent via pin sdi, presents right channel or left channel audio data. via pin sclk the bit clock for the serial bit-stream is sig- nalled. sdo and lrck are synchronous with sclk. sdo is an output; lrck and sck are inputs; sdi is not used. the volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5db each. the gain can be set from C34.5db to +12db. the stage is set to mute by default. if the adc output is not enabled, the volume settings are set to their default values. changing the volume and mute control can only be done after enabling the input. the i2s output uses the same clocks as the i2s input. the sampling rate therefore depends also on the input sampling rate. the exact ratio can be set in register 11h. the sdo output can be configured to operate in push/pull (3 different driver strengths) or to be tri-state. for a more detailed description of the gpio functionality of this pin please refer to chapter gpio pins on page 50 . o ver current limit hpr/hpl pins hpcm pin, @1.8v 70ma 110ma ma ma over current limit hpr/hpl pins hpcm pin, @2.7v 140ma 220ma ma ma p srrhp power supply rejection ratio 200hz-20khz, 720mvpp, rl=16 90 db a hpmute mute attenuation 100 db table 14. headphone related register name base offset description out_r 2-wire serial 02h r ight hp output volume and over-current settings out_l 2-wire serial 03h l eft hp output volume settings, enable and detection control audioset2 2-wire serial 15h au to fading timing settings audioset3 2-wire serial 16h po wer options, common mode buffer enable irqenrd_3 2-wire serial 26h i nterrupt settings for over current and hp detection table 13. headphone output parameter (continued) symbol parameter condition min typ max unit ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 24 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - a u d i o f u n c t i o n s 8.5.3 i2s modes the afe can be operated either in slave mode or in slave mode with the master clock directly signalled via pin mclk. the master clock (mclk) is the necessary internal over-sampling clock for the dac and adc (e.g. 128*fs, fs=audio sampling frequency) in slave mode the pll generates the master clock based on lrck. thus the pll needs to be preset to the expected sampling frequency. the ranges are 8ks-23ks (8khz-23khz) and 24ks-48ks (24khz-48khz). please refer to register 1a-7h. figure 11. i2s modes 8.5.4 clock supervision the digital audio interface automatically checks the lrck. an interrupt can be generated when the state of the lrck input changes. a bit in the interrupt register represents the actual state (present or not present) of the lrck. 8.5.5 signal description the digital audio interface uses the standard i2s format: left justified msb first one additional leading bit the on-chip synchronization circuit allows any bit-count up 32bit. when there are less than 18 bits sampled, the data sample is completed with 0s. in i2s direct mode the data length has to be minimum 18 bits. the adc output is always 14 bit. if more sclk pulses are provided, only the first 14 will be significant. all following bits will be 0. sclk has not to be necessarily synchronous to lrck but the high going edge has to be separate from lrck edges. the lrck signal has to be derived from a jitter-free clock source, because the on-chip pll is generating a clock for the digital filter, which has to be always in correct phase lock condition to the external lrck. please observe that lrck has to be activated before enabling the adc. ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 25 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - a u d i o f u n c t i o n s figure 12. i2s left justified mode 8.5.6 parameter dvdd=2.9v, t a =25c, slave mode, f s =48khz, mclk = 128*f s, unless otherwise specified table 15. i2s timing symbol parameter condition min typ max unit t sclk sclk cycle time 160 ns t sclkh sclk pulse width high 80 ns t sclkl sclk pulse width low 80 ns t lrsu lrck setup time before sclk rising edge 80 ns t lrhd lrck hold time after sclk rising edge 80 ns t sdsu sdi setup time before sclk rising edge 25 ns t sdhd sdi hold time after sclk rising edge 25 ns t sdod sdo delay from sclk falling edge 25 ns t jitter jitter of lrck internal pll generates mclk from lrck -20 20 ns i2s direct mode t scd sclk delay after mclk rising edge 0.5 1.5 ns t lrd lrlck delay after sclk rising edge 0.5 1.5 ns t sdsu sdi setup time before sclk rising edge 5 ns t sdhd sdi hold time after sclk rising edge 5 ns t sdod sdo delay from sclk falling edge 15 ns ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 26 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - a u d i o f u n c t i o n s 8.5.7 register description dac and adc have to be enabled in register 14h first before other settings in register 0eh to 11h can be programmed. 8.6 audio output mixer 8.6.1 general the mixer stage sums up the audio signals of the following stages microphone input 1 line input 1/2 dac output adc input the mixing ratios have to be set within the volume registers of the corresponding input stages. please be sure that the peak voltage of input signals for the mixer stage is less than avdd17/3. if summing up several signals, each individual signal has of course to be accordingly lower. this shall insure that the output signal is also not higher than avdd17/3 peak to get a proper signal for the output amplifier. this stage features an automatic gain control (agc), which automatically avoids clipping. 8.6.2 register description table 16. audio converter related register name base offset description dac_r 2-wire serial 0eh d ac input volume settings dac_l 2-wire serial 0fh d ac input volume settings adc_r 2-wire serial 10h ad c output volume settings, source multiplexer settings adc_l 2-wire serial 11h ad c output volume settings, sampling rate settings dac_if 2-wire serial 11h d ac input digital volume settings audioset1 2-wire serial 14h en able/disable dac, dac gain stage & adc audioset3 2-wire serial 16h en able/disable mixer input out_cntr3 2-wire serial 1a-3h c ontrol of sdo signal and drive pll 2-wire serial 1a-7h pl l sample rate settings pmu_enable 2-wire serial 1ch enables writings to extended register s 1ah-3 and 1ah-7 irqenrd_1 2-wire serial 25h i nterrupt settings for lrck changes table 17. audio mixer related register name base offset description audioset2 2-wire serial 15h en able/disable mixer stage and agc audioset3 2-wire serial 16h en able/disable dac, mic or line inputs to mixer stage ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 27 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - a u d i o f u n c t i o n s 8.7 2-wire-serial control interface 8.7.1 general there is an i2c slave block implemented to have access to 64 byte of setting information. the i2c address is: adr_group8 - audio processors 8ch_write 8dh_read 8.7.2 protocol figure 13. byte write figure 14. page write byte write and page write formats are used to write data to the slave. the transmission begins with the start condition, which is generated by the master when the bus is in idle state (the bus is free). the device-write address is followed by the word address. after the word address any number of data bytes can be sent to the slave. the word address is incremented internally, in order to write subsequent data bytes on subsequent address locations. table 18. 2-wire serial symbol definition symbol definition rw note s start condition after stop r 1 bit sr repeated start r 1 bit dw device address for write r 1000 1100b (8ch) dr device address for read r 1000 1101b 8dh) wa word address r 8 bit a acknowledge w 1 bit n no acknowledge r 1 bit reg_data register data/write r 8 bit data (n) register data/read w 8 bit p stop condition r 1 bit wa++ increment word address internally r during acknowledge AS3543 (=slave) receives data AS3543 (=slave) transmits data ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 28 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - a u d i o f u n c t i o n s for reading data from the slave device, the master has to change the transfer direction. this can be done either with a repeated start condition followed by the device-read address, or simply with a new transmission start followed by the device-read address, when the bus is in idle state. the device-read address is always followed by the 1st register byte transmitted from the slave. in read mode any number of subsequent register bytes can be read from the slave. the word address is incremented internally. figure 15. random read random read and sequential read are combined formats. the repeated start condition is used to change the direction after the data transfer from the master. the word address transfer is initiated with a start condition issued by the master while the bus is idle. the start condition is followed by the device-write address and the word address. in order to change the data direction a repeated start condition is issued on the 1st scl pulse after the acknowl- edge bit of the word address transfer. after the reception of the device-read address, the slave becomes the transmit- ter. in this state the slave transmits register data located by the previous received word address vector. the master responds to the data byte with a not-acknowledge, and issues a stop condition on the bus. figure 16. sequential read sequential read is the extended form of random read, as more than one register-data bytes are transferred subse- quently. in difference to the random read, for a sequential read the transferred register-data bytes are responded by an acknowledge from the master. the number of data bytes transferred in one sequence is unlimited (consider the behavior of the word-address counter). to terminate the transmission the master has to send a not-acknowledge fol- lowing the last data byte and generate the stop condition subsequently. figure 17. current address read to keep the access time as small as possible, this format allows a read access without the word address transfer in advance to the data transfer. the bus is idle and the master issues a start condition followed by the device-read address. analogous to random read, a single byte transfer is terminated with a not-acknowledge after the 1st register byte. analogous to sequential read an unlimited number of data bytes can be transferred, where the data bytes has to be responded with an acknowledge from the master. for termination of the transmission the master sends a not- acknowledge following the last data byte and a subsequent stop condition. ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 29 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - a u d i o f u n c t i o n s 8.7.3 parameter figure 18. 2-wire serial timing dvdd =2.9v, t amb =25oc; unless otherwise specified table 19. 2-wire serial parameter symbol parameter condition min typ max unit v csl cscl, csda low input level (max 30%dvdd) 0 - 0.87 v v csh cscl, csda high input level cscl, csda (min 70%dvdd) 2.03 - 5.5 v hyst cscl, csda input hysteresis 200 450 800 mv v ol csda low output level at 3ma - - 0.4 v tsp spike insensitivity 50 100 - ns t h clock high time max. 400khz clock speed 500 ns t l clock low time max. 400khz clock speed 500 ns t su csda has to change tsetup before rising edge of cscl 250 - - ns t hd no hold time needed for csda relative to rising edge of cscl 0 - - ns ts csda h hold time relative to csda edge for start/stop/rep_start 200 - - ns t pd csda prop delay relative to lowgoing edge of cscl 50 ns ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 30 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - p o w e r m a n a g e m e n t f u n c t i o n s 9 detailed description - power management functions 9.1 low drop out regulators 9.1.1 general these ldos are designed to supply sensitive analogue circuits, audio devices, ad and da converters, micro-control- ler and other peripheral devices. the design is optimized to deliver the best compromise between quiescent current and regulator performance for battery powered devices. stability is guaranteed with ceramic output capacitors of 1 f +/-20% (x5r) or 2.2 f +100/-50% (z5u). the low esr of these caps ensures low output impedance at high frequencies. regulation performance is excellent even under low dropout conditions, when the power transistor has to operate in linear mode. power supply rejection is high enough to suppress high ripple on the battery at the output. the low noise performance allows direct connection of noise sensi- tive circuits without additional filtering networks. the low impedance of the power device enables the device to deliver up to 150ma even at nearly discharged batteries without any decrease of performance. figure 19. ldo block diagram 9.1.2 ldo1 this ldo generates the audio supply voltage used for the afe itself. input voltage is vdd17in output voltage is avdd17 (typ. 1.7v) driver strength: 50ma it is set to a default output voltage of 1.7v, 50ma max . it supplies the analog audio blocks of the afe. additional external loads are possible but most not exceed the supply ratings in total together with the operating internal blocks. further the external load must not induce noise to the sensitive avdd17 supply pin. 9.1.3 ldo2 this ldo generates the digital and audio supply voltage used for the afe itself. input voltage is bvdd output voltage is avdd27 (typ. 2.7v) driver strength: 100ma, can be programmed to 200ma it is set to a default output voltage of 2.7v, 100ma max . it supplies the digital part of the afe as well as all audio switches and multiplexers. additional external loads are possible but most not exceed the supply ratings in total together with the operating internal blocks. further the external load must not induce noise to the avdd27 supply pin but is not as critical as avdd17. ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 31 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - p o w e r m a n a g e m e n t f u n c t i o n s 9.1.4 ldo3 & ldo4 these ldos can be used to generate the periphery voltage for the digital processor or other external components (e.g. ext. dac, usb-phy, sd-cards, nand-flashes, fm-tuner ) ldo3 has a separate input pin (bvddp1) which can be connected to either the battery or a dcdc converter output. input voltage bvddp1 or bvdd output voltage is pvdd1 & pvdd2 (1.2 to 3.5v) default value at start-up is defined by vprg2 pin driver strength: 100ma, can be programmed to 200ma 9.1.5 parameter bvdd=3.6v, t a = 25 o c, unless otherwise mentioned table 20. ldo parameter symbol parameter condition min typ max unit r on on resistance 1 psrr power supply rejection ratio f=1khz 70 db f=100khz 40 i off shut down current 100 na i vdd supply current without load 50 a noise output noise 10hz < f < 100khz 50 v rms t start startup time 200 s v out_tol output voltage tolerance minimum +/ 50mv 2.5% 2.5% mv v linereg line regulation ldo2, static <1 mv ldo2, transient; slope: t r =10s <10 v loadreg load regulation ldo2, static <1 mv ldo2, transient; slope: t r =10s <10 i limit current limitation ldo1 100 ldo2, ldo3, ldo4 200 ma ldo2, ldo3 and ldo4, has to be enabled via register 18h1, 18h2, 18h3 350 ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 32 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - p o w e r m a n a g e m e n t f u n c t i o n s figure 20. ldo block diagram 9.1.6 register description load regulation output noise transient load: 1ma C 100ma slope: 1s output load: 150ma load regulation load regulation output load: 10ma transient input voltage ripple: 500mv output load: 150ma transient input voltage ripple: 500mv table 21. ldo related register name base offset description pvdd1 2-wire serial 18h-1 pvdd1 (ldo3) control and voltage set tings pvdd2 2-wire serial 18h-2 pvdd2 (ldo4) control and voltage set tings avdd27 2-wire serial 18h-6 avdd27 (ldo2) control and voltage s ettings avdd17 2-wire serial 18h-7 avdd17 (ldo1) control and voltage s ettings pmu_enable 2-wire serial 1ch enables writings to extended register s 18h-1 to 18h-7 ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 33 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - p o w e r m a n a g e m e n t f u n c t i o n s 9.2 dcdc step-down converter (2x) 9.2.1 general these converters are meant to convert the battery voltage down to voltages which fit to the core and peripheral supply voltage requirements for microprocessors. input voltage bvddc1/2 (usually connected to the battery) output voltage cvdd1 & cvdd2 output voltage levels can be programmed independently form 0.61v to 3.35v the default value at start-up is defined by vprg1 and vprg2 pin dvm for both outputs with selectable timings driver strength 250ma under- and over-voltage detection figure 21. dcdc step-down block diagram 9.2.2 functional description the step-down converter is a high efficiency fixed frequency current mode regulator. by using low resistance internal pmos and nmos switches efficiency up to 97% can be achieved. the fast switching frequency allows using small inductors, without increasing the current ripple. the unique feedback and regulation circuit guarantees optimum load and line regulation over the whole output voltage range, up to an output current of 250ma, with an output capacitor of only 10 m f. the implemented current limitation protects the dcdc and the coil during overload condition. to achieve optimized performance in different applications, adjustable settings allow to compromise between high effi- ciency and low input, output ripple: ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 34 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - p o w e r m a n a g e m e n t f u n c t i o n s low ripple, low noise operation: in this mode there is no minimum coil current necessary before switching off the pmos. as result, the on time of the pmos will be reduced down to tmin_on at no or light load conditions, even if the coil current is very small or the coil current is inverted. this results in a very low ripple and noise, but decreased efficiency, at light loads, especially at low input to output voltage differences. in the case of an inverted coil current the regulator will not operate in pulse skip mode. figure 22. dcdc buck with disabled current force / pulse skip mode 1: lxc1 voltage, 2:coil current (1mv=1ma) 3: output voltage high efficiency operation: in this mode there is a minimum coil current necessary before switching off the pmos. as result, fewer pulses at low output loads are necessary, and therefore the efficiency at low output load is increased. on the other hand the output voltage ripple increases, and the noisy pulse skip operation is on up to a higher output current. figure 23. dcdc buck with enabled current force / pulse skip mode 1: lxc1 voltage, 2:coil current (1mv=1ma) 3: output voltage its also possible to switch between these two modes dynamically during operation: 100% pmos on mode for low dropout regulation: for low input to output voltage difference the dcdc converter can use 100% duty cycle for the pmos transistor, which is than in ldo mode. this feature is enabled if the output voltage drops by more than 4%. ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 35 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - p o w e r m a n a g e m e n t f u n c t i o n s 9.2.3 parameter bvdd=3.6, t a = 25 o c, unless otherwise mentioned figure 24. dcdc step-down performance characteristics table 22. dcdc parameter symbol parameter condition min typ max unit v in input voltage bvdd 2.7 5.5 v v out regulated output voltage 0.65 3.4 v v out_tol output voltage tolerance minimum +/- 50mv -3% 3% mv i load maximum load current 250 ma i limit current limit 450 ma r psw p-switch on resistance bvdd=3.0v 0.5 0.7 r nsw n-switch on resistance bvdd=3.0v 0.5 0.7 f sw switching frequency depending on dcdc_cntr settings 1/2 mhz f swsc switching frequency in shortcut case 0.6 mhz c out output capacitor ceramic, +/- 10% tolerance 10 f lx inductor +/- 10% tolerance 2.2 4.7 h eff efficiency iout=100ma, vout=3.0v 97 % i vdd current consumption operating current without load low power mode current shutdown current 220 100 0.1 a t min_on minimum on time 80 ns t min_off minimum off time 40 ns v linereg line regulation static 2 mv transient; slope: t r =10 s, 100mv step, 200ma load 10 v loadreg load regulation static 5 mv transient; slope: t r =10 s, 100ma step 50 efficiency vs. output current 70 7 5 80 85 90 95 100 0,1 1 10 100 1000 output current [ma] efficiency [%]? v in =3.6v v out =3.0v v out =1.8v v out =1.2v ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 36 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - p o w e r m a n a g e m e n t f u n c t i o n s 9.2.4 register description table 23. dcdc buck related register name base offset description cvdd1 2-wire serial 17h-1 cvdd1 (dcdc1) voltage settings cvdd2 2-wire serial 17h-2 cvdd2 (dcdc2) voltage settings hibernation 2-wire serial 17h-6 hibernation control dcdc_cntr 2-wire serial 17h-7 dcdc frequency and dvm settings pmu_enable 2-wire serial 1ch enables writings to extended register s 17h-1 to 17h-7 output voltage vs. output current 1,175 1 ,185 1,195 1,205 1,215 1,225 0 50 100 150 200 250 output current [ma] output voltage [v]? v in =3.6v line regulation 1,195 1,2 1,205 1,21 1,215 3 3,4 3,8 4,2 4,6 5 input voltage [v] output voltage [v]? v out =1.2v i out =0ma i out =125ma i out =250ma ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 37 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - p o w e r m a n a g e m e n t f u n c t i o n s 9.3 15v step-up dcdc converter 9.3.1 general the integrated step-up dc/dc converter is a high efficiency current-mode pwm regulator, providing an output volt- age up to 15v. a constant switching-frequency results in a low noise on supply and output voltages. it has two programable high voltage current sinks (1.2 to 37.2ma) for driving e.g. white leds as back-light. it can drive also unbalanced strings due to the internal automatic feedback selection. a voltage feedback mode allows generating constant supply voltages for e.g. oleds by using an external zener diode. to bias the diode isink1 is sinking about 50ua in this voltage feedback mode. an internal protection circuit will shut down the regulator if the voltage on sw15 exceeds 15v. no more external pro- tection has to be used to avoid an exceeding of the operation conditions in a no load situation. 9.3.2 dimming the dcdc booster together with the current sinks has an adjustable automatic logarithmic dimming for a smooth on/ off transition. it is also possible to control the dimming with an external signal via a gpio pin. pwgd, q24m or q32k pin can be selected as input for the external dimming signal. 9.3.3 current sink only mode the current sinks are normally only working when the dcdc booster is switched on, but can also be activated sepa- rately. to do so reg. 1bh-1 has to be set to 08h (select external dimming), and reg. 1ah-4 has to be set to xxxx xx00b (no ext. dimming source selected). figure 25. dcdc15 block diagram ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 38 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - p o w e r m a n a g e m e n t f u n c t i o n s 9.3.4 parameter bvdd=3.6v, t a = 25 o c, unless otherwise mentioned figure 26. 15v step-up performance characteristics table 24. dcdc parameter symbol parameter condition min typ max unit v sw high voltage pin pin sw15 0 15 v i vdd quiescent current pulse skipping mode 140 a v fb feedback voltage, transient pin isink1 or isink2 0 5.5 v v fb feedback voltage, during regulation pin isink1 or isink2 0.63 v i sw_max current limit v15_on = 1 350 510 750 ma r sw switch resistance v15_on = 0 0.85 1.54 w i load load current @ 15v output voltage 0 45 ma i fb current into isink1 during voltage feedback mode 50 ua v pulseskip pulseskip threshold voltage at pin isink1 or isink2, pulse skips are introduces when load current becomes too low 0.96 v f in fixed switching frequency 0.45 0.66 0.85 mhz c out output capacitor ceramic 1 f l (inductor) i load > 20ma use inductors with small c parasitic (<100pf) for high efficiency 17 22 27 h i load < 20ma 8 10 27 t min_on minimum ontime guaranteed per design 90 200 ns mdc maximum duty cycle guaranteed per design 84 91 98 % efficiency vs. output current 70 75 80 85 90 95 1 10 100 output current [ma] efficiency [%] ? v in =3.6v load = 3 leds ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 39 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - p o w e r m a n a g e m e n t f u n c t i o n s 9.3.5 register description 9.4 charger 9.4.1 general this block can be used to charge a 4v li-ion accumulator. it supports constant current and constant voltage charging modes with adjustable charging currents (55 to 460ma) and maximum charging voltage (3.9 to 4.25v). an internal protection circuit will limit the charging current when a chgin voltage drop is detected. for the end of charge current four levels can be selected while the battery temperature shutdown has two temperature levels to choose from. the current battery voltage as well as the actual charging current can be measured with the general purpose adc. figure 27. charger block diagram table 25. dcdc15 related register name base offset description in_cntr 2-wire serial 1ah-4 selection of external dimming input dcdc15 2-wire serial 1bh-1 dcdc15 on/off and dimming control isink1 2-wire serial 1bh-2 isink1 current settings isink2 2-wire serial 1bh-3 isink2 current settings pmu_enable 2-wire serial 1ch enables writings to extended register s 1ah1, 1bh-1 to 1bh-3 ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 40 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - p o w e r m a n a g e m e n t f u n c t i o n s figure 28. charger states 9.4.2 soft charge if the battery and therefore chgout is below 3v the charger is working in a fixed soft charge mode with the smallest possible charging current of 55ma and 3.9v charger end voltage. after reaching the 3v level the charger switches to the register defined mode and sets the programmed charging current and voltage. 9.4.3 end of charge detection for the eoc level 4 presets can be selected. this makes it possible to monitor the charging progress also during con- stant voltage mode. if the eoc level is reached an interrupt can be generated, but it is also possible to poll the charger status bits at any time. 9.4.4 temperature supervision this charger block also features a 15ua supply for an external 100k ntc resistor to measure the battery temperature while charging. if the temperature is too high, an interrupt can be generated. if the battery temperature drops the char- ger will start charging again. the levels for switching off/on the charger (45/42c or 55/50c) can be selected via reg- ister settings. if the ntc resistor does not have 100k its value can be corrected with a resistor in series or in parallel. 9.4.5 parameter avdd27=2.7, t a = 25 o c, unless otherwise mentioned table 26. charger parameter symbol parameter condition min typ max unit i chg (0-7) charging current bvdd > 2.7v, i chg > 60ma i nom -8% i nom i nom +8% ma v chg (0-7) charging voltage bvdd > 2.7v, end of charge is true v nom -50mv v nom v nom +30mv v v on_abs charger on voltage irq chgout>3v 3.1 4.0 v v on_rel charger on voltage irq chgin-chgout 170 240 mv v off_rel charger off voltage irq chgin-chgout 40 77 mv ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 41 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - p o w e r m a n a g e m e n t f u n c t i o n s 9.4.6 register description v batemp_on battery temp. high level (45 or 55c) bvdd >3v 610 or 400 mv v batemp_off battery temp. low level (42 or 50c) bvdd >3v 700 or 500 mv i chg_off end of charge current level bvdd >3v 5% i nom 10% 30% 50% 70% i nom 15% i nom ma i rev_off reverse current shut down bvdd = 5v, chgin open <1 ua table 27. charger related register name base offset description chgvbus1 2-wire serial 19h-1h charger voltage, current and temp . supervision control chgvbus2 2-wire serial 19h-2h charger temperature and eoc level settings pmu_enable 2-wire serial 1ch enables writings to extended register s 19h-1 to 19h-2 irqenrd_2 2-wire serial 25h enable/disable eoc and battery over-te mperature interrupt read out charger status irqenrd_4 2-wire serial 27h set chgin debounce time adc10_0 2-wire serial 2eh adc source selection, adc result<9:8> adc10_1 2-wire serial 2fh adc result <7:0> t able 26. charger parameter symbol parameter condition min typ max unit ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 42 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - p o w e r m a n a g e m e n t f u n c t i o n s 9.5 battery switch 9.5.1 general an integrated battery switch provides a battery separation during charging. in normal battery operation the switch is closed. with an ideal diode function a smooth transition between the different modes are guaranteed. figure 29. battery switch modes ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 43 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - s y s t e m f u n c t i o n s 10 detailed description - system functions 10.1 system 10.1.1 general the system block handles the power up, power down and regulator voltage settings of the afe. the pwgd and xres outputs can be configured to operate in push/pull (2 different driver strengths) open-drain mode or to be tri-state. for a more detailed description of the gpio functionality of these pins please refer to chapter gpio pi ns on page 50 . 10.1.2 power up/down conditions the chip powers up when one of the following condition is true: the chip automatically shuts off if one of the following conditions arises: table 28. power up conditions # source description 1 pwrup pwup on_key high level at prwup pin of >= 1/3 bvdd 2 chgin pwup charger plug-in high level at chgin pin of >= 4.0v 3 vbus pwup usb plug-in . high level at vbus pin of >= 4.5v 4 wakeup pwup wake-up timer power-up on rtc clock 4 mclk pwup on_key high level at mclk pin of >= 1/3 bvdd table 29. power down conditions # source description 1 serif major pwdn power-down by serif writing 0h to register 20h this power-down clears wake-up as well. 2 emergency pwdn power-down if pwrup pin is high for 10sec. this time can be reduced to 5sec with bit 7 in register 21h. 3 wake-up pwdn write 4h to reg. 1ch and 0h to reg. 1ah disable heartbeat source write 3 times to reg.22h to define wake-up time; power-down by heartbeat without source by writing 9h to reg. 20h 4 heartbeat pwdn write 4h to reg. 1ch and 4h/8h or ch to reg. 1ah select hbt source write 9h to reg. 20h enable heartbeat with source power-down if no edge on the selected hbt source is seen for 500ms. 5 serif watch-dog pwdn write 3h to reg. 20h enable serif watch-dog power-down if no serif read is seen for 500ms. 6 junction-temp pwdn power-down if junction temperature rises up to 140degc. this threshold can be lowered with bits <4:0> in reg 21h. this supervisor can be disabled with bit 2 in reg. 20h. 7 bvdd low pwdn power-down if avdd27 ldo has 10% under-voltage for more than 680us. this supervisor can get disabled with bit 6 in reg. 21h. 8 pvdd1 low pwdn power-down if enabled with bit 1 in reg. 23h and pvdd1 ldo has 10% under-voltage for more than 680us. 9 pvdd2 low pwdn power-down if enabled with bit 3 in reg. 23h and pvdd2 ldo has 10% under-voltage for more than 680us. 10 cvdd1 low pwdn power-down if enabled with bit 7 in reg. 23h and cvdd1 dcdc has 10% under-voltage for more than 680us. 11 cvdd2 low pwdn power-down if enabled with bit 1 in reg. 24h and cvdd2 dcdc has 10% under-voltage for more than 680us. ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 44 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - s y s t e m f u n c t i o n s 10.1.3 start-up sequence the afe offers different power-up sequences. while vprg1 and vprg2 pins are defining the regulator voltages vprg3 is setting the sequence of powering on the regulators during the start-up. these pins detect 5 logical input states which shall come from an external resistor divider network. at first, ldo2 (avdd27) and ldo1 (avdd17) are powered up. this cannot be influenced with the selection of specific sequences below. ldo2 is necessary for the internal supply of the afe, ldo1 could be turned off later if no audio functionality is needed. after power-up sequence all voltage settings and power on/off conditions of the described regulators can be pro- grammed via the serial interface 10.1.4 xres delay with pwgd pin with using an exteral capacitor on pwgd, the xres signal can be delayed. this delay can be calculated with the 10ua pull-up current and a comparator threshold of ~1v. using a 100nf capacitance will give a delay of 10ms. table 30. start-up sequence cvdd1 cvdd2 pvdd1 pvdd2 vprg1 (core) vdd 0.8v 150k pu 1 1. pull ups (pu) must be connected to avdd27 1.5v open 1.2v 150k pd 2 2. pull downs (pd) shall be connected to dvss vss 1.0v vprg2 (peri) vdd 2.5v 3.3v 3.3v 150k pu 2.8v 1.8v 3.3v open 1.8v 3.3v 3.3v 150k pd vss 3.3v 3.3v 3.3v vprg3 (sequence) vdd 1 st 2 nd 3 rd off 150k pu 1 st 2 nd 3 rd 3 rd open 3 rd 2 nd 1 st 1 st 150k pd vss 3 rd 2 nd 1 st off ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 45 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - s y s t e m f u n c t i o n s 10.1.5 register description 10.2 hibernation 10.2.1 general hibernation allows shutting down a part or the complete system. hibernation can be terminated by every possible interrupt of the afe. e.g. one can use the rtc for a time triggered wake-up. the interrupt has to be enabled before going to hibernation.: 10.2.2 register description table 31. system related register name base offset description out_cntr1 2-wire serial 1a-1h c ontrol of pwgd and xres signal and drive in_cntr 2-wire serial 1a-4h se lection of hbt input pin pmu_enable 2-wire serial 1ch enables writings to extended register s 1ah-1 and 1ah-5 system 2-wire serial 20h w atchdog and over-temperature control, power down enable supervisor 2-wire serial 21h se t emergency shutdown time irqenrd_0 2-wire serial 23h en able/disable pmu interrupts irqenrd_1 2-wire serial 24h en able/disable wake-up, voice and pmu interrupts irqenrd_2 2-wire serial 25h en able/disable charger, usb and supervisor interrupts irqenrd_3 2-wire serial 26h en able/disable junction temperature interrupt table 32. hibernation state description enter to enter hibernation mode the following settings have to be done: - enable just these irq sources which should lead to leave hibernation mode. - make sure that irq is inactive (irq flags get cleared by reg0x23-27 readings. - define which regulators should be kept powered and enter hibernation by writing to reg 1ch_0x06 + reg 17h_0xxx note that hibernation will shutdown regulators which are not in the keep list of the mentioned reg 17h writing and which are powered by the selected power-up sequence. (e.g. pvdd2 will not go hibernation with vprg3 is vss or vdd) hibernation vdd27 chip supply is kept on all other regulators are switched off dependent on the keep-bits xres goes active and pwgd goes inactive. leave the chip will come out of hibernation with irq activation. start-up sequence is provided defined by the vprg state latched on the previous start-up. (vprg state does not get latched again by leaving hibernation) table 33. hibernation related register name base offset description hibernation 2-wire serial 17h-6 h ibernation control pmu_enable 2-wire serial 1ch en ables writings to extended register 17h-6 ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 46 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - s y s t e m f u n c t i o n s 10.3 supervisor 10.3.1 general this supervisor function can be used for automatic detection of bvdd brown out or junction over-temperature condi- tion. 10.3.2 bvdd supervision the bvdd supervision interrupt level is set to 175mv above regulator output avdd27. when bvdd reaches this level an interrupt can be generated. if avdd27 reaches the programmed level of avdd27 -10% for more than 680us, the afe shuts down automatically, if the shutdown is not disabled. 10.3.3 junction temperature supervision the temperature supervision level can also be set by 5 bits (120 to C15oc). if the temperature reaches this level, an interrupt can be generated. the over-temperature shutdown level is always 20oc higher. 10.3.4 power rail monitoring the 4 main regulators as well as the dcdc15 booster and the system supply avdd27 have an extra monitor which observes the output voltage of the regulators. this power rail monitors are independent from the 10bit adc. to activate these please see related registers. for a shut down the voltage of the regulator has to be 10% or more below the pro- grammed value for more than 680us. 10.3.5 register description 10.4 interrupt generation 10.4.1 general all interrupt sources can get enabled or disabled by corresponding bits in the 5 irq-bytes. by default no interrupt source is enabled. the xirq output can be configured to operate in push/pull (2 different driver strengths), open-drain mode or to be tri- state. the signal polarity can be defined as active-low or active-high. default state is open-drain active-low. for a more detailed description of the gpio functionality of this pin please refer to chapter gpio pins on page 50 . 10.4.2 irq source interpretation there are 3 different modules to process interrupt sources: level the irq output is kept active as long as the interrupt source is present and this irq-bit is enabled edge the irq gets active with a high going edge of this source. the irq stays active until the corresponding irq-register gets read. table 34. supervisor related register name base offset description supervisor 2-wire serial 21h l ow battery shutdown disable and junction temperature supervision threshold levels irqenrd_0 2-wire serial 23h en able/disable pvdd/cvdd monitoring interrupt and shutdown irqenrd_1 2-wire serial 24h en able/disable pvdd/cvdd monitoring interrupt and shutdown irqenrd_2 2-wire serial 25h en able/disable battery brown out interrupt irqenrd_3 2-wire serial 26h en able/disable junction temperature interrupt irqenrd_4 2-wire serial 27h en able/disable avdd27 and dcdc15 monitoring interrupt ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 47 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - s y s t e m f u n c t i o n s status change the irq gets active when the source-state changes. the change bit and the status can be read to notice which inter- rupt was the source. the irq stays active until the corresponding interrupt register gets read. 10.4.3 de-bouncer there is a de-bounce function implemented for usb and charger. since these 2 signals can be unstable for the phase of plug-in or unplug, a de-bounce time of 512ms/256ms/128ms/8ms can be selected by 2 bits in the irq_enrd_4 register (27h). 10.4.4 interrupt sources 26 irq events will activate the xirq pin: headphone connected headphone over-current microphone connected microphone remote control voice activation threshold reached rtc sec/min elapsed 10bit adc end of conversion i2s changed (active/inactive) usb changed (connect/disconnect) charger changed (end of charge or connect/disconnect) battery temperature high (at 45oc or 55oc with 100k w ntc) junction temperature high rtc watchdog (e.g. after battery was changed) battery low (brown-out voltage reached) wake-up from hibernation power-up key (pin pwrup) pressed power rail monitor: over-voltage pvdd1, pvdd2, cvdd1, cvdd2, dcdc15 power rail monitor: under-voltage pvdd1, pvdd2, cvdd1, cvdd2, avdd27 10.4.5 register description table 35. interrupt related register name base offset description out_cntr3 2-wire serial 1a-3h c ontrol of xirq signal, polarity and drive pmu_enable 2-wire serial 1ch enables writings to extended register 1ah-3 and 1ah-5 irqenrd_0 2-wire serial 23h en able/disable pmu interrupts irqenrd_1 2-wire serial 24h en able/disable wake-up, voice and pmu interrupts irqenrd_2 2-wire serial 25h en able/disable charger, usb and supervisor interrupts irqenrd_3 2-wire serial 26h en able/disable junction temperature, headphone, microphone and i2s interrupt irqenrd_4 2-wire serial 27h en able/disable pmu, rtc, adc10 and microphone interrupt, set vbus and chgin debounce time ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 48 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - s y s t e m f u n c t i o n s 10.5 real time clock 10.5.1 general the real time clock block is an independent block, which is still working even when the chip is shut down. the only condition for this operation is that bvddr has a voltage of above 1.0v. the block uses a standard 32khz crystal that is connected to a low power oscillator. the total power consumption is typ. 650na. (q32k clock buffer not operating) an internal supply switch will supply the rtc as long as possible form the li-ion battery and only switch to bvddr if the main battery is empty or has been removed. the rtc seconds counter is 32bit wide and can be programmed via the 2-wire serial interface. the rtc can deliver a second or minute interrupt. another 23bit wide counter allows auto wake-up (max. after 96 days). this counter is internally connected to the power-up and hibernation control block. the rtc voltage regulator (rvdd) further supplies a 128bit sram. it can be used to store settings or data before shutdown. the q32k output can be configured to operate in push/pull (3 different driver strengths) or to be trie-state. for a more detailed description of the gpio functionality of this pin please refer to chapter gpio pins on page 50 . 10.5.2 clock adjustment the rtc clock is adjustable in steps of 7.6ppm which allows the use of inexpensive 32khz crystals. the nominal fre- quency shall be 32.768hz. this frequency is divided down to 0.25hz: f = 32.768 / (4*32*1024) at the input of this divider one can add corrective counts, which allow to correct an inaccurate crystal in a range from C 64 counts (=-488ppm) to +63 counts (=+480ppm): f corrected = f crystal / [(4*32*1024)-64+rtc_tbc] 10.5.3 register description table 36. rtc related register name base offset description ram & wakeup 2-wire serial 19h rtc wake-up settings and sdram access out_cntr2 2-wire serial 1a-2h c ontrol of q32k signal and drive pmu_enable 2-wire serial 1ch enables writings to extended register 1ah-2 irqenrd_2 2-wire serial 25h interrupt settings for rvdd under-vol tage detection irqenrd_4 2-wire serial 27h interrupt settings for getting a sec ond or minute interrupt rtc_cntr 2-wire serial 28h rtc oscillator and counter enable, f ree usable bits rtc_time 2-wire serial 29h rtc interrupt and time correction se ttings rtc_0 to rtc_3 2-wire serial 2ah to 2 dh rtc time-base seconds registers ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 49 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - s y s t e m f u n c t i o n s 10.6 10-bit adc 10.6.1 general this general purpose adc can be used for measuring several voltages and currents to perform functions like battery monitor, temperature supervision, button press detection, etc. 10.6.2 input sources 10.6.3 parameter avdd27=2.7, t a = 25 o c, unless otherwise mentioned table 37. adc10 input sources # source range lsb description 0 bvdd 5.120v 5mv check main system input voltage 1 bvddr 5.120v 5mv check rtc backup battery voltage 2 chgin 5.120v 5mv check charger input voltage 3 chgout 5.120v 5mv check battery voltage of 4v li-ion accumulator 4 vbus 5.120v 5mv check usb input voltage 5 5.120v 5mv source defined by dc_test in register 18h 6 battemp 2.048v 2mv check battery charging temperature 7 reserved 8 mics 2.048v 2mv check voltage on mics for remote control or external voltage measurement 9 reserved a i_mics 1.024ma typ. 2ua check current of mics for remote control detection b reserved c vbe_1ua 1.024 1mv measuring basis-emitter voltage of temperature sense transistor; tj = (674 - adc10<9:0>) / 2 d vbe_2ua 1.024 1mv measuring basis-emitter voltage of temperature sense transistor; tj = (694 - adc10<9:0>) / 2 e i_chgact 1.024v 1mv check active charger current f i_chgref 1.024v 1mv check reference charger current table 38. adc10 parameter symbol parameter condition min typ max unit adc fs adc full scale range 2.16 v t con conversion time - 34 50 s i_mic fs i_mics full scale range 0.7 1.0 1.4 ma ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 50 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - s y s t e m f u n c t i o n s 10.6.4 register description 10.7 gpio pins 10.7.1 general pwgd, xres, q24m, q32k, sdo, xirq are so called gpio (general purpose inputs/outputs) as they can feature auxiliary functionality. if the main pin function is not needed all pins can provide internal clocks or can drive a static high or low. four differ- ent clock lines (clkint1, clkint2, clk24m, clk32k) can be selected. each of these clock lines can drive different frequencies which can be set by register options. in addition some pins can provide a pwm signal. the duty cycle of the pwm output can also be set in the registers. pwgd, xres and xirq can be configured also as open drain outputs. for all pins the driver strength of the push/pull output mode can be selected. pwgd, q24m, q32k can also be used as inputs for a heartbeat signal or an external dimming signal for the dcdc15 booster. 10.7.2 internal source signals clkint1 signal this is an internal signal line which can drive pre defined frequencies of 125hz, 1khz, 667khz or 2mhz. this signal line can be selected as source for the xres, q24m, q32k, xirq and sdo gpio output pins. clkint2 signal this is an internal signal line which can drive the pll clock, the clock for the logarithmic dimming of dcdc15 or can be set to static high/low. this signal line can be selected as source for the pwgd, q24m, q32k and xirq output pins. clk24m signal this is an internal signal line which is driving the 12-24mhz oscillator output clock per default, but can be set to drive this clock divided by 2 or 4. the forth option is to deactivate the 12-24mhz oscillator. clk32k signal this is an internal signal line which is driving the 32khz oscillator output clock per default, but can be set to drive also a 1hz signal as well as a a static high/low. pwm signal the duty cycle of the pwm signal can be set in 128 steps plus an option to invert the signal. it ca be used as source for all gpio outputs other than xirq. 10.7.3 pin functions pwgd pin can drive clk24m, clkint2 or the pwm signal as auxiliary function. the output can be configured to operate in push/pull (2 different driver strength) open-drain mode or to be trie-state. it can be used as an input for a heartbeat, external dimming signal or as additional source for the 10-bit general purpose adc. using a capacitor on this pin will delay the xres signal. please refer to chapter xres delay with pwgd pin on page 4 4 . when usig the pin as an adc input the voltage to be measurted has to be higher than 1v, the xres delay function- ality is than no longer avilable. table 39. adc10 related register name base offset description pmu_enable 2-wire serial 1ch extended adc source selection irqenrd_4 2-wire serial 27h interrupt settings for end of conver sion interrupt adc10_0 2-wire serial 2eh adc source selection, adc result<9:8> adc10_1 2 wire serial 2fh adc result <7:0> ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 51 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - s y s t e m f u n c t i o n s xres pin can drive clk32k, clkint1 or the pwm signal as auxiliary function. the output can be configured to operate in push/ pull (2 different driver strengths) open-drain mode or to be trie-state. the xres signal can be delayed by using a capacitor on pwgd pin. please refer to chapter xres delay with pwgd p in on page 44 . q24m pin can drive clkint1, clkint2 or the pwm signal as auxiliary function. the output can be configured to operate in push/pull (3 different driver strengths) or to be trie-state. it can be used as an input for a heartbeat or external dimming signal. q32k pin can drive clkint1, clkint2 or the pwm signal as auxiliary function. the output can be configured to operate in push/pull (3 different driver strengths) or to be trie-state. it can be used as an input for a heartbeat or external dimming signal. xirq pin can drive clkint1, clkint2 signal as auxiliary function. the output can be configured to operate in push/pull (2 dif- ferent driver strengths) open-drain mode or to be trie-state. the interrupt signal polarity can be defined as active-low or active-high. sdo pin can drive clk24m, clkint1 or the pwm signal as auxiliary function. the output can be configured to operate in push/pull (3 different driver strengths) or to be trie-state. 10.7.4 register description 10.8 12-24mhz oscillator 10.8.1 general this oscillator can be used to generate a system clock for e.g. a microprocessor if needed. it is not needed for any other afe function. as the oscillator is default on, it has to be disabled if not needed. 10.8.2 register description table 40. gpio related register name base offset description out_cntr1 2-wire serial 1a-1h c ontrol of pwgd and xres signal and drive out_cntr2 2-wire serial 1a-2h c ontrol of q32k signal and drive out_cntr3 2-wire serial 1a-3h c ontrol of xirq signal, polarity and drive in_cntr 2-wire serial 1a-4h se lection of hbt and dcdc 15 dimming input pin clk_cntr 2-wire serial 1a-5h se lection of clock source or drive level for gpio pins pwm_cntr 2-wire serial 1a-6h pw m duty cycle and polarity settings pmu_enable 2-wire serial 1ch enables writings to extended register s 1ah-1 to 1ah-6 table 41. 12-24mhz oscillator related register name base offset description clk_cntr 2-wire serial 1a-5h en able/disable oscillator and clock divider settings pmu_enable 2-wire serial 1ch enables writings to extended register s a1ah-5 ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 52 - 91 AS3543 3v2 data sheet - d e t a i l e d d e s c r i p t i o n - s y s t e m f u n c t i o n s 10.9 unique id code (64 bit otp rom) 10.9.1 general this fuse array is used to store a unique identification number, which can be used for drm issues. the number is gen- erated and programmed during the production process. 10.9.2 register description table 42. uid related register name base offset description uid_0 to uid_7 2-wire serial 38h to 3fh unique id register 0 to 7 ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 53 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n 11 register definition table 43. i2c register overview addr name b7 b6 b5 b4 b3 b2 b1 b0 audio registers 00h reserved 01h reserved 02h out_r lout 0: hp; 1: lout mux_c<1:0> 0: sum; 1: dac; 2: lin1(2); 3: mic outr_vol<4:0> gain from mux_c to hpr/loutr= -40.5db...+6db 0 3h out_l mute_k_on stage_on hpdet_on o utl_vol<4:0> gain from mux_c to hpl/loutl= -40.5db+6db 0 4h reserved 05h reserved 06h mic_r mic_mode 0: monodiff 1: singleend pre_gain<1:0> 0: 30db; 1: 36db; 2: 42db; 3: reserved micr_vol<4:0> gain from micamp (n4) to mixer (n12) = -40.5db...+6d b 07h mic_l msup_off mute_d_on - micl_vol<4:0> gain from micamp (n4) to mixer (n13) = -40.5db...+6d b 08h reserved 09h reserved 0ah line_in_r li_hiq 0: lowpwr 1: hiquality mux_e 0: lin1 1: lin2 mute_b_off lir_vol<4:0> gain from mux_e (n27) to mixer (n10) = -40.5db...+6d b 0bh line_in_l lo_dischg_o f f li_mode 0: stereo 1: mono mute_g_off lil_vol<4:0> gain from mux_e (n28) to mixer (n17) = -40.5db...+6d b 0ch reserved 0dh reserved 0eh dac_r - - - dar_vol<4:0> gain from dac (n19) to mixer (n23) = -40.5db+6db 0 fh dac_l - - mute_h_off d al_vol<4:0> gain from dac (n22) to mixer (n26) = -40.5db+6db 1 0h adc_r mux_a<1:0> 0: mic; 1: lin1; 2: lin2; 3: sum - adr_vol<4:0> gain from mux_a to adc/mixer (n9) = -34.5db...+12db 1 1h adc_l adc_mode<1:0> 0: fdac/2; 1: fdac/4; 2,3: fdac/1 mute_a_off adl_vol<4:0> gain from mux_a to adc/mixer (n18) = -34.5db...+12db ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 54 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n 12h dac_if i2s_direct i2s_loop i 2s_atten 0: noatten 1: attenon sdi_atten<4:0> attenuation of i2s input data = -48db...-1.5db 1 3h reserved 14h audioset1 adc_on dac_on dac_gst_on - - lin_on - mic_on 15h audioset2 bias_off sum_off s um_agc_of f sum_hp_hiq gain_step<1:0> 0: 2ms; 1: 4ms; 2: 8ms; 3: no control vmics<1:0> 0: vdd17*20/17, 1: vdd17*20/22 2: vdd17*20/27, 3: vdd17*20/32 16h audioset3 - micmix_off - adcmix_on linmix_off h p_faststar t hp_bias 0: *1 1: *1.5 hpcm_on pmu register 1 7h-1 cvdd1 prog_cvdd1 v sel_cvdd1>6:0> 0 off 0x01 C 0x40: 0.6v + vsel * 12.5mv -> (0.6125v C 1.400v) 0x41 C 0x70: 1.4v + (vsel-0x40) * 25mv ->(1.425v C 2.600v) 0x71 C 0x7f: 2.6v + (vsel-0x70) * 50mv -> (2.650v C 3.350v) 17h-2 cvdd2 prog_cvdd2 v sel_cvdd2<6:0> 0 off 0x01 C 0x40: 0.6v + vsel * 12.5mv -> (0.6125v C 1.400v) 0x41 C 0x70: 1.4v + (vsel-0x40) * 25mv ->(1.425v C 2.600v) 0x71 C 0x7f: 2.6v + (vsel-0x70) * 50mv -> (2.650v C 3.350v) 17h-3 reserved 17h-4 reserved 17h-5 reserved 17h-6 hibernation - keep_pvdd2 keep_pvdd1 - - - keep_cvdd2 keep_cvdd1 17h-7 dcdc_cntr cvdd2_fast 0: cext=10uf 1: cext=22uf cvdd1_fast 0: cext=10uf 1: cext=22uf cvdd2_freq 0: 2mhz 1: 1mhz cvdd1_freq 0: 2mhz 1: 1mhz dvm_cvdd2<1:0> 0: immediate; 1: 42us/step; 2: 166us/step; 3: 666us/step dvm_cvdd1<1:0> 0: immediate; 1: 42us/step; 2: 166us/step; 3: 666us/step 18h-1 pvdd1 pvdd1_off i lim_h_pvdd1 0: 100ma 1: 200ma prg_pvdd1 vsel_pvdd1<4:0> 0x00 C 0x0f: 1.2v + vsel * 50mv -> (1.2v C 1.95v) 0x10 C 0x1f: 2.0v + (vsel-0x10) * 100mv ->(2.0v C 3.5v) 18h-2 pvdd2 pvdd2_off i lim_h_pvdd2 0: 100ma 1: 200ma prg_pvdd2 vsel_pvdd2<4:0> 0x00 C 0x0f: 1.2v + vsel * 50mv -> (1.2v C 1.95v) 0x10 C 0x1f: 2.0v + (vsel-0x10) * 100mv ->(2.0v C 3.5v) 18h-3 reserved 18h-4 reserved 18h-5 reserved table 43. i2c register overview addr name b7 b6 b5 b4 b3 b2 b1 b0 ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 55 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n 18h-6 avdd27 - ilim_h_vdd27 0: 100ma 1: 200ma prg_avdd27 - vsel_avdd27<3:0> 0x0 C 0x2: 2.3v 0x3 C 0xf: 2.0v + vsel* 100mv ->(2.3v C 3.5v) 18h-7 avdd17 avdd17_off - prg_avdd17 v sel_avdd17<4:0> 0x00 C 0x1f: 1.65v + vsel * 50mv -> (1.65v C 3.2v) 19h-1 chgvbus1 bat_temp_of f c hg_i<2:0> 0..3: 55, 70, 140, 210ma 4..7: 280, 350, 420, 460ma chg_v<2:0> 3.9v + chg_v * 50mv -> (3.9v C 4.25v) chg_off 19h-2 chgvbus2 vbus_comp_th <1:0> 0: 4.5v; 1: 3.18v; 2: 1.5v; 3: 0.6v - - - bat_temp 0: 0.4/0.5v; 1: 0.6/0.7v chg_eoc_th<1:0> 0: 10% cc; 1: 30% cc; 2: 50% cc; 3: 70% cc 1ah-1 out_cntr1 drive_pwgd<1:0> 0: 6ma od; 1: 6ma pp; 2: 1ma pp; 3: hiz mux_pwgd<1:0> 0: pwgd; 1: clk24m; 2: clkint2; 3: pwm drive_xres<1:0> 0: 6ma od; 1: 6ma pp; 2: 1ma pp; 3: hiz mux_xres<1:0> 0: xres; 1: clk32k; 2: clkint1; 3: pwm 1ah-2 out_cntr2 drive_q24m<1:0> 0: 6ma pp; 1: hiz; 2: 2ma pp; 3: 1ma pp mux_q24m<1:0> 0: clk24m; 1: clkint1; 2: clkint2; 3: pwm drive_q32k<1:0> 0: 6ma pp; 1: hiz; 2: 2ma pp; 3: 1ma pp mux_q32k<1:0> 0: clk32k; 1: clkint1; 2: clkint2; 3: pwm 1ah-3 out_cntr3 drive_sdo<1:0> 0: 6ma pp; 1: hiz; 2: 2ma pp; 3: 1ma pp mux_sdo<1:0> 0: sdo; 1: clk24m; 2: clkint1; 3: pwm drive_xirq<1:0> 0: 6ma od; 1: 6ma pp; 2: 1ma pp; 3: hiz mux_xirq<1:0> 0: xirq; 1: clkint1; 2: clkint2; 3: irq 1ah-4 in_cntr - - - - mux_hbt<1:0> 0: off; 1: pwgd; 2: q24m; 3: q32k mux_extdim<1:0> 0: off; 1: pwgd; 2: q24m; q32k 1ah-5 clk_cntr clkint2<1:0> 0: clkpll; 1: clklogdim; 2: low; 3: high clkint1<1:0> 0: 2mhz; 1: 667khz; 2: 1khz; 3: 125hz clk24m<1:0> 0: osc24m; 1: osc24m_div2; 2: osc24m_div4; 3: osc24m_pd clk32k<1:0> 0: osc32k; 1: 1hz; 2: low; 3: high 1ah-6 pwm_cntr pwm_invert p wm_cycle<6:0> 0: no pulses; 1-127: duty cycle = pwm_cycle * 0.39% 1ah-7 pll osr<3:0> 0x0: 128; 0x1-0xf: n/a vco_mode<1:0> 0: 24-48khz; 1: 8-23khz; 2: 49-96khz; 3: n/a pll_mode<1:0> 0: automatic; 1: on; 2: off; 3: auto_inv 1bh-1 dcdc15 dim_up_xdo w n dim_rate<1:0> 0: 0ms; 1: 300ms; 2: 600ms; 3: 1200ms vfb_on extdim_on - - - 1 bh-2 isink1 i_sink1<4:0> 0: off; 1-31: 1.2ma *i;_isink1 -> (1.2ma...37.2ma) 1bh-3 isink2 i_sink2<4:0> 0: off; 1-31: 1.2ma *i;_isink2 -> (1.2ma...37.2ma) table 43. i2c register overview addr name b7 b6 b5 b4 b3 b2 b1 b0 ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 56 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n 1ch pmu_enable dc_test_mux <3:0> 0: open; 1: avdd27; 2: avdd17; 3: pvdd1; 4: pvdd2; 5: cvdd1; 6: cvdd2; 7: rvdd; 8: fvdd; 9: pwgd; a-f: not defined pmu_gate pmu_wr_enable <2:0> subregister addresses for registers: 0x17: dcdc regulators 0x18: ldos regulators 0x19: charger 0x1a: io_clock_control 0x1b: backlight_dcdc system register 20h system design_version<3:0> h b_wd_on jtemp_off i2c_wd_on pwr_hold 21h supervisor sd_time 0: 10s; 1: 5s bvddlow_sd_ off vdd27-10% - jtemp_sup<4:0> temp_shutdown = 140c - jtemp_sup*5c -> (140c...- 15c) temp_irq = 120c - jtemp_sup*5c -> (120c...-35c) 22h ram & wakeup 1st write/read: wake_up_byte_0 128s 64s 32s 16s 8s 4s 2s 1s 2nd write/read: wake_up_byte_1 32ks 16ks 8ks 4ks 2ks 1ks 512s 256s 3rd write/read: wake_up_byte_2 wakeup_ on 4ms 2ms 1ms 512ks 256ks 128ks 64ks 4th to 19th write/read: non volatile memory bytes<0:15> sram_128<0:15> 23h irqenrd_0 cvdd1_sd cvdd1_irq - - pvdd2_sd pvdd2_irq pvdd1_sd pvdd1_irq c vdd1_under cvdd1_over - - pvdd2_under pvdd2_over pvdd1_under pvdd1_over 24h irqenrd_1 pwrup_irq wakeup_irq mclk_irq - - - cvdd2_sd cvdd2_irq c vdd2_under cvdd2_over 25h irqenrd_2 battemp_irq - - chg_irq - usb_irq rtc_wd bvdd_low c hg_eoc chg_con chg_changed usb_con usb_changed 26h irqenrd_3 jtemp_high - hp_ovc - i2s_irq voxm_irq mic_con hph_con i 2s_status i2s_changed 27h irqenrd_4 t_deb<1:0> 0: 512ms; 1: 256ms; 2: 128ms; 3: 8ms avdd27_irq dcdc15_irq - rem_det rtc_update adc_eoc a vdd27_under dcdc15_over 28h rtc_cntr free_bits<3:0> to be used for application purpose - rtc_on osc_on 29h rtc_time irq_min trtc<6:0> 2ah rtc_0 qrtc<7:0> t able 43. i2c register overview addr name b7 b6 b5 b4 b3 b2 b1 b0 ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 57 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n 2bh rtc_1 qrtc<15:8> 2ch rtc_2 qrtc<23:16> 2dh rtc_3 qrtc<31:24> 2eh adc10_0 adc10_mux<3:0> 0: bvdd; 1: bvddr; 2: chgin; 3: chgout; 4: vbus 5: dc_test; 6: battemp; 7: mclk; 8: mics; a: i_mics; c: vbe_1ua; d: vbe_2ua; e: i_chgact; f: i_chgref - - adc10<9:8> 2fh adc10_1 adc10<7:0> uid register 3 8h uid_0 id<7:0> 39h uid_1 id<15:8> 3ah uid_2 id<23:16> 3bh uid_3 id<31:24> 3ch uid_4 id<39:32> 3dh uid_5 id<47:40> 3eh uid_6 id<55:48> 3fh uid_7 id<63:56> table 43. i2c register overview addr name b7 b6 b5 b4 b3 b2 b1 b0 ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 58 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n table 44. out_r register name base default out_r 2-wire serial 00h offset: 02h right hp/line output register configures mux_c and the audio gain from mux_c output to hpr/loutr output and switches between the headphone and line output. this register is reset when the block is disabled in audioset1 register (14h) or at a avdd27-por. the register cannot be written when the block is disabled. bit bit name default access bit description 7 lout 0 r/w switches between headphone and line output 00: headphone enabled 01: line out enabled 6:5 mux_c<1:0> 00 r/w multiplexes the analog audio inputs to mux_c output for hpr/l and loutr/l 00: mixer: r to hpr/loutr and l to hpl/loutl 01: dac direct : (n19/ n22), dac gain stage and mixer are bypassed 10: linein direct (n10/n17) 11: mic direct (n12/n13) 4:0 outr_vol<4:0> 00000 r/w volume settings for right headphone/line output, adjustable in 32 steps @ 1.5db; gain from mux_c to hpr/loutr 11111: 6 db gain 11110: 4.5 db gain .. 00001: -39 db gain 00000: -40.5 db gain table 45. out_l register name base default out_l 2-wire serial 00h offset: 03h left hp/line output register configures the audio gain from mux_c output to hpl/loutl output and controls mute switch k as well as on/off of the stage. this register is reset when the stage is disabled in audioset1 register (14h) or at a avdd27-por. the register cannot be written when the block is disabled bit bit name default access bit description 7 mute_k_on 0 r/w control of mute switch k 0: hp/line output set to mute 1: normal operation 6 stage_on 0 r/w 0: hp/line stage not powered 1: normal operation 5 hpdet_on 0 r/w enables the detection when a headset gets connected. hpcm is used as a sense pin and is biased to 150mv 0: no headphone detection 1: enable headphone detection 4:0 outl_vol<4:0> 00000 r/w volume settings for left headphone/line output, adjustable in 32 steps @ 1.5db; gain from mux_c to hpl/loutrl 11111: 6 db gain 11110: 4.5 db gain .. 00001: -39 db gain 00000: -40.5 db gain ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 59 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n table 46. mic_r register name base default mic_r 2-wire serial 00h offset: 06h right microphone input register configures mux_c and the audio gain from mux_c output to hpr/loutr output and switches between the headphone and line output. this register is reset at a avdd27-por. bit bit name default access bit description 7 mic_mode 0 r/w selects the microphone input mode 0: mono differential mode 1: single ended mode 6:5 pre_gain<1:0> 00 r/w sets the gain of the microphone preamplifier (gain from microphone inputs to n3) 00: gain set to 30 db 01: gain set to 36 db 10: gain set to 42 db 11: reserved, do not use. 4:0 micr_vol<4:0> 00000 r/w volume settings for right microphone input, adjustable in 32 steps @ 1.5db; gain from microphone amplifier (n4) to mixer input (n12) 11111: 6 db gain 11110: 4.5 db gain .. 00001: -39 db gain 00000: -40.5 db gain table 47. mic_l register name base default mic_l 2-wire serial 00h offset: 07h left microphone input register configures the gain from microphone amplifier output up to mixer input ( ) and controls mute switch d. this register is reset at a avdd27-por. bit bit name default access bit description 7 msup_off 0 r/w 0: microphone supply enabled 1: microphone supply disabled 6 mute_d_on 0 r/w control of mute switch d 0: normal operation 1: microphone input set to mute 5 - 0 n/a 4:0 micl_vol<4:0> 00000 r/w volume settings for left microphone input, adjustable in 32 steps @ 1.5db; gain from microphone amplifier (n4) to mixer input (n13) 11111: 6 db gain 11110: 4.5 db gain .. 00001: -39 db gain 00000: -40.5 db gain ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 60 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n table 48. line_in_r register name base default line_in_r 2-wire serial 00h offset: 0ah right line input register configures the gain from right analog line input mux e to mixer input ( ) and controls mute switch b. this register is reset when the block is disabled in audioset1 register (14h) or at a avdd27-por. the register cannot be written when the block is disabled. bit bit name default access bit description 7 li_hiq 0 r/w 0: line input set to low power mode 1: line input set to high quality mode 6 mux_e 0 r/w selects the line input 0: mux_e output connected to line input 1 1: mux_e output connected to line input 2 5 mute_b_off 0 r/w control of mute switch b 0: right line input is set to mute 1: normal operation 4:0 lir_vol<4:0> 00000 r/w volume settings for right line input, adjustable in 32 steps @ 1.5db; gain from mux output (n27) to mixer input (n10) 11111: 6 db gain 11110: 4.5 db gain .. 00001: -39 db gain 00000: -40.5 db gain table 49. line_in_l register name base default line_in_l 2-wire serial 00h offset: 0bh left line input register configures the gain from analog left line input mux e to mixer input ( ) and controls mute switch g. this register is reset when the block is disabled in audioset1 register (14h) or at a avdd27-por. the register cannot be written when the block is disabled. bit bit name default access bit description 7 lo_dischg_off 0 r/w 0: normal operation 1: disables discharge resitors. need if the line ouptut is directly connected to the line input for useing the same connector. 6 li_mode 0 r/w selects the line input mode 0: stereo 1: 2x mono single ended 5 mute_g_off 0 r/w control of mute switch g 0: left line input is set to mute 1: normal operation 4:0 lil_vol<4:0> 00000 r/w volume settings for left line input, adjustable in 32 steps @ 1.5db; gain from mux output (n28) to mixer input (n17) 11111: 6 db gain 11110: 4.5 db gain .. 00001: -39 db gain 00000: -40.5 db gain ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 61 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n table 50. dac_r register name base default dac_r 2-wire serial 00h offset: 0eh right dac output register configures the gain from dac output to mixer input ( ). this register is reset when the block is disabled in audioset1 register (14h) or at a avdd27-por. the register cannot be written when the block is disabled. bit bit name default access bit description 7:5 - 000 n/a 4:0 dar_vol<4:0> 00000 r/w volume settings for right dac output, adjustable in 32 steps @ 1.5db; gain from dac output (n19) to mixer input (n23) 11111: 6 db gain 11110: 4.5 db gain .. 00001: -39 db gain 00000: -40.5 db gain table 51. dac_l register name base default dac_l 2-wire serial 00h offset: 0fh left dac output register configures the gain from dac output to mixer input ( ) and controls mute switch h. this register is reset when the block is disabled in audioset1 register (14h) or at a avdd27-por. the register cannot be written when the block is disabled. bit bit name default access bit description 7:6 - 00 n/a 5 mute_h_off 0 r/w control of mute switch h 0: dac output is set to mute 1: normal operation 4:0 dal_vol<4:0> 00000 r/w volume settings for left dac output, adjustable in 32 steps @ 1.5db; gain from dac output (n22) to mixer input (n26) 11111: 6 db gain 11110: 4.5 db gain .. 00001: -39 db gain 00000: -40.5 db gain ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 62 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n table 52. adc_r register name base default adc_r 2-wire serial 00h offset: 10h right adc input register configures mux_a and the gain from mux_a output to the adc/mixer input ( ). this register is reset when the block is disabled in audioset1 register (14h) or at a avdd27-por. the register cannot be written when the block is disabled. bit bit name default access bit description 7:6 mux_a<1:0> 00 r/w connect mux a output to following inputs 00: microphone (n4/n4) 01: line_in1 (n1/n8) 10: line_in2 (n2/n7) 11: mixer output (n24/n25) 5 - 0 n/a 4:0 adr_vol<4:0> 00000 r/w volume settings for right adc input, adjustable in 32 steps @ 1.5db; gain from mux a output to adc/mixer input ( ) (n9) 11111: 12 db gain 11110: 10.5 db gain .. 00001: -33 db gain 00000: -34.5 db gain table 53. adc_l register name base default adc_l 2-wire serial 00h offset: 0fh left adc input register configures the adc mode, gain from mux_a output to the adc/mixer input ( ) input and controls mute switch a. this register is reset when the block is disabled in audioset1 register (14h) or at a avdd27-por. the register cannot be written when the block is disabled. bit bit name default access bit description 7:6 adc_mode<1:0> 00 r/w devider setting for adc sampling frequency 00: i2s lrck / 2 01: i2s lrck / 4 10: i2s lrck 11: i2s lrck 5 mute_a_off 0 r/w control of mute switch a 0: adc input is set to mute 1: normal operation 4:0 adl_vol<4:0> 00000 r/w volume settings for left adc input, adjustable in 32 steps @ 1.5db; gain from mux a output to adc/mixer input ( ) (n18) 11111: 6 db gain 11110: 4.5 db gain .. 00001: -39 db gain 00000: -40.5 db gain ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 63 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n table 54. dac_if register name base default dac_if 2-wire serial 00h offset: 12h dac interface register configures the dac interface and digital gain on the i2s input stream. this register is reset at a avdd27-por. bit bit name default access bit description 7 i2s_direct 0 r/w 0: i2s master clock is generated by the internal pll 1: signal on mclk is used as i2s master clock 6 i2s_loop 0 r/w 0: normal operation 1: adc output is connected to dac input 5 i2s_atten 0 r/w 0: normal operation 1: digital attenuation on i2s input data (sdi) enabled 4:0 sdi_atten<4:0> 00000 r/w digital volume settings i2s input data (sdi), adjustable in 32 steps @ 1.5db; gain from sdi pin to dac input 11111: -1.5 db gain 11110: -3 db gain .. 00001: -46.5 db gain 00000: -48.0 db gain table 55. audioset1 register name base default audioset1 2-wire serial 00h offset: 14h first audio set register powers the various audio inputs and outputs up or down. caution: this control register resets and holds linein, dac, and adc related regis- ters in reset. after activation the required register settings need to be re- programmed. this register is reset at a avdd27-por. bit bit name default access bit description 7 adc_on 0 r/w 0: adc powered down 1: adc enabled for recording 6 dac_on 0 r/w 0: dac powered down 1: dac enabled for playback 5 dac_gst_on 0 r/w 0: dac gainstage powered down 1: dac gainstage enabled (needed for playback via mixer) 4:3 - 00 n/a 2 lin_on 0 r/w 0: line input powered down 1: line input enabled 1 - 0 n/a 0 mic_on 0 r/w 0: microphone input powered down 1: microphone input enabled ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 64 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n table 56. audioset2 register name base default audioset2 2-wire serial 00h offset: 15h second audio set register control of various audio blocks. this register is reset at a avdd27-por. bit bit name default access bit description 7 bias_off 0 r/w power-down of the agnd bias if only digital data transfer and pmu functions are used. 0: bias enabled 1: bias disabled, for power saving in non audio mode 6 sum_off 0 r/w 0: mixer stage enabled 1: mixer stage powered down 5 sum_agc_off 0 r/w switches the signal limiter off (n20/n21) 0: automatic gain control for summing stage enabled 1: automatic gain control for summing stage disabled 4 sum_hp_hiq 0 r/w 0: mixer and headphone stage in low power mode 1: mixer and headphone stage in high quality mode 3:2 gain_step<1:0> 00 r/w sets the transition time of the auto fading for the output stage 00: 2ms/step 01: 4ms/step 10: 8ms/step 11: auto fading off 1:0 vmics<1:0> 00 r/w sets the microphone supply output voltage 00: avdd17*20/17 01: avdd17*20/22 10: avdd17*20/27 11: avdd17*20/32 table 57. audioset3 register name base default audioset3 2-wire serial 00h offset: 16h third audio set register control of mixer stage inputs and headphone. this register is reset at a avdd27-por. bit bit name default access bit description 7 - 0 n/a 6 micmix_off 0 r/w 0: microphone input to r and l (n12/n13) on 1: microphone input to mixer disabled 5 - 0 n/a 4 adcmix_on 0 r/w 0: adc input to mixer disabled 1: adc input to r and l (n12/n13) on 3 linmix_off 0 r/w 0: line input to r and l (n12/n13) on 1: line input to mixer disabled 2 hp_faststart 0 r/w 0: normal operation 1: shortens delay for start-up when using 220nf on hpgnd 1 hp_bias 0 r/w 0: 100% 1: 150%, increased bisas for lower noise and thd 0 hpcm_on 0 r/w 0: headphone common mode buffer is switched off 1: headphone common mode buffer is powerd up ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 65 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n table 58. cvdd1 register name base default cvdd1 2-wire serial 00h offset: 17h-1 cvdd1 dc/dc buck regulator control register this is an extended register and needs to be enabled by writing 001b to reg. 1ch first. this register is reset at a avdd27-por. bit bit name default access bit description 7 prog_cvdd1 0 r/w selects the control mode for cvdd1 0: cvdd1 is in default mode controlled by pin vprg1 1: cvdd1 is register controlled (reg. 17-1h) 6:0 vsel_cvdd1>6:0> 000000 r/w the voltage select bits set the dc/dc output voltage level and power the dc/dc converter down. 00h: dc/dc powered down 01h-40h: cvdd1=0.6v+vsel_cvdd1*12.5mv 41h-70h: cvdd1=1.4v+(vsel_cvdd1-40h)*25mv 71h-7fh: cvdd1=2.6v+(vsel_cvdd1-70h)*50mv table 59. cvdd2 register name base default cvdd2 2-wire serial 00h offset: 17h-2 cvdd2 dc/dc buck regulator control register this is an extended register and needs to be enabled by writing 010b to reg. 1ch first. this register is reset at a avdd27-por. bit bit name default access bit description 7 prog_cvdd2 0 r/w selects the control mode for cvdd2 0: cvdd2 is in default mode controlled by pin vprg2 1: cvdd2 is register controlled (reg. 17-1h) 6:0 vsel_cvdd2<6:0> 000000 r/w the voltage select bits set the dc/dc output voltage level and power the dc/dc converter down. 00h: dc/dc powered down 01h-40h: cvdd1=0.6v+vsel_cvdd2*12.5mv 41h-70h: cvdd1=1.4v+(vsel_cvdd2-40h)*25mv 71h-7fh: cvdd1=2.6v+(vsel_cvdd2-70h)*50mv ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 66 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n table 60. hibernation register name base default hibernation 2-wire serial 00h offset: 17h-6 pmu hibernation control register hibernation starts when writing this register. this is an extended register and needs to be enabled by writing 110b to reg. 1ch first. this register is reset at a avdd27-por. bit bit name default access bit description 7 - 0 n/a 6 keep_pvdd2 0 r/w keeps the programmed pvdd2 level during hibernation. 0: power down pvdd2 1: keep pvdd2 5 keep_pvdd1 0 r/w keeps the programmed pvdd1 level during hibernation. 0: power down pvdd1 1: keep pvdd1 4:2 - 000 n/a 1 keep_cvdd2 0 r/w keeps the programmed cvdd2 level during hibernation. 0: power down cvdd2 1: keep cvdd2 0 keep_cvdd1 0 r/w keeps the programmed pvdd1 level during hibernation. 0: power down cvdd1 1: keep cvdd1 table 61. dcdc_cntr register name base default dcdc_cntr 2-wire serial 00h offset: 17h-7 dc/dc step down control register this is an extended register and needs to be enabled by writing 111b to reg. 1ch first. this register is reset at a avdd27-por. bit bit name default access bit description 7 cvdd2_fast 0 r/w selects a faster regulation mode for cvdd2 suitable for larger load changes. 0: normal mode, cext=10uf 1: fast mode, cext=22uf required 6 cvdd1_fast 0 r/w selects a faster regulation mode for cvdd1 suitable for larger load changes. 0: normal mode, cext=10uf 1: fast mode, cext=22uf required 5 cvdd2_freq 0 r/w selects the switching frequency for dcdc2 0: 2mhz 1: 1mhz 4 cvdd1_freq 0 r/w selects the switching frequency for dcdc2 0: 2mhz 1: 1mhz ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 67 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n 3:2 dvm_cvdd2<1:0> 00 r/w configures the dynamic voltage management (output voltage slope) for cvdd2 00: immediate change of the output voltage 01: 42us/step 02:166us/step 03: 666us/step 1:0 dvm_cvdd1<1:0> 00 r/w configures the dynamic voltage management (output voltage slope) for cvdd1 00: immediate change of the output voltage 01: 42us/step 02:166us/step 03: 666us/step table 62. pvdd1 register name base default pvdd1 2-wire serial 00h offset: 18h-1 pvdd1 control register this is an extended register and needs to be enabled by writing 001b to reg. 1ch first. this register is reset at a avdd27-por. bit bit name default access bit description 7 pvdd1_off 0 r/w switches off pvdd1 regulator 0: normal mode 1: pvdd1 switched off 6 ilim_h_pvdd1 0 r/w selects the higher current limit for pvdd1 0: default mode, 100ma 1: 200ma mode 5 prg_pvdd1 0 r/w selects the output voltage control mode for pvdd1 0: pvdd1 is in default mode controlled by pin vprg2 1: pvdd1 is register controlled (reg. 18-1h) 4:0 vsel_pvdd1<4:0> 00000 r/w sets the ldo output voltage in register control mode (default voltage of the regulator is selcted by pin vprog2) 0x00-0x0f: 1.2v+vsel*50mv ->(1.2v - 1.95v) 0x10-0x1f: 2.0v + (vsel-0x10)*100mv -> (2.0v-3.5v) table 61. dcdc_cntr register name base default dcdc_cntr 2-wire serial 00h offset: 17h-7 dc/dc step down control register this is an extended register and needs to be enabled by writing 111b to reg. 1ch first. this register is reset at a avdd27-por. bit bit name default access bit description ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 68 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n table 63. pvdd2 register name base default pvdd2 2-wire serial 00h offset: 18h-2 pvdd2 control register this is an extended register and needs to be enabled by writing 010b to reg. 1ch first. this register is reset at a avdd27-por. bit bit name default access bit description 7 pvdd2_off 0 r/w switches off pvdd2 regulator 0: normal mode 1: pvdd1 switched off 6 ilim_h_pvdd2 0 r/w selects the higher current limit for pvdd2 0: default mode, 100ma 1: 200ma mode 5 prg_pvdd2 0 r/w selects the output voltage control mode for pvdd2 0: pvdd2 is in default mode controlled by pin vprg2 1: pvdd2 is register controlled (reg. 18-2h) 4:0 vsel_pvdd2<4:0> 00000 r/w sets the ldo output voltage in register control mode (default voltage of the regulator is selcted by pin vprg2) 0x00-0x0f: 1.2v+vsel*50mv ->(1.2v - 1.95v) 0x10-0x1f: 2.0v + (vsel-0x10)*100mv -> (2.0v-3.5v) table 64. avdd27 register name base default avdd27 2-wire serial 00h offset: 18h-6 avdd27 control register this is an extended register and needs to be enabled by writing 110b to reg. 1ch first. this register is reset at a avdd27-por. bit bit name default access bit description 7 - 0 n/a 6 ilim_h_vdd27 0 r/w selects the higher current limit for avdd27 0: default mode, 100ma 1: 200ma mode 5 prg_avdd27 0 r/w selects the output voltage control mode for avdd27 0: avdd27 is in default mode (2.7v) 1: avdd27 is register controlled (reg. 18-6h) 5 - 0 n/a 3:0 vsel_avdd27<3:0> 0000 r/w sets the ldo output voltage in register control mode (default voltage of the regulator is 2.7v) 0x0-0x2: 2.3v 0x3-0xf: 2.0v + vsel*100mv -> (2.3v-3.5v) ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 69 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n table 65. avdd17 register name base default avdd17 2-wire serial 00h offset: 18h-7 avdd17 control register this is an extended register and needs to be enabled by writing 111b to reg. 1ch first. this register is reset at a avdd27-por. bit bit name default access bit description 7 avdd17_off 0 r/w switches off avdd17 regulator 0: normal mode 1: avdd17 switched off, no audio functions possible 6 - 0 n/a 5 prg_avdd17 0 r/w selects the output voltage control mode for avdd17 0: avdd17 is in default mode (1.7v) 1: avdd17 is register controlled (reg. 18-7h) 4:0 vsel_avdd17<4:0> 0000 r/w sets the ldo output voltage in register control mode (default voltage of the regulator is 1.7v) 0x00-0x1f: 1.65v + vsel*100mv -> (1.65v-3.2v) table 66. chgvbus1 register name base default chgvbus1 2-wire serial 00h offset: 19h-1 charger / vbus 1 control register this is an extended register and needs to be enabled by writing 001b to reg. 1ch first. this register is reset at a avdd27-por. bit bit name default access bit description 7 bat_temp_off 0 r/w 0: enables 15ua supply for external 100k ntc resistor 1: disables supply 6:4 chg_i<2:0> 000 r/w set maximum charging current during constant current charging 111: 460 ma 110: 420 ma 101: 350 ma 100: 280 ma 011: 210 ma 010: 140 ma 001: 70 ma 000: 55 ma 3:1 chg_v<2:0> 000 r/w set maximum charger voltage in 50mv steps for the constant voltage charging 111: 4.25 v 110: 4.2 v .. 001: 3.95 v 000: 3.9 v 0 chg_off 0 r/w 0: enables charger 1: disables charger ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 70 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n table 67. chgvbus2 register name base default chgvbus2 2-wire serial 00h offset: 19h-2 charger / vbus 2 control register this is an extended register and needs to be enabled by writing 010b to reg. 1ch first. this register is reset at a avdd27-por. bit bit name default access bit description 7:6 vbus_comp_th <1:0> 00 r/w sets the threshold for the vbus comparator. the output can be read in register 25h. 00: 4.5v 01: 3.18v 10: 1.5v 11: 0.6v 5:3 - 000 n/a - 2 bat_temp 0 r/w selects the battery temperature supervision level 0: 0.4/0.5v equal to 55/50c with 100k ntc 1: 0.6/0.7v equal to 45/42c with 100k ntc 1:0 chg_eoc_th<1:0> 00 r/w setes the threshold for the charger eoc (end of charge) interrupt as a ratio of the constant current (cc) setting. 00: 10% cc 01: 30% cc 10: 50% cc 11: 70% cc table 68. out_cntr1 register name base default out_cntr1 2-wire serial 00h offset: 1ah-1 pwgd and xres output control register this is an extended register and needs to be enabled by writing 001b to reg. 1ch first. this register is reset at a avdd27-por. bit bit name default access bit description 7:6 drive_pwgd<1:0> 00 r/w sets the pwgd output pin to open-drain, push-pull or tri-state and sets various driving strengths 00: 6ma open-drain output 01: 6ma push-pull output 10: 1ma push-pull output 11: hiz, stri-state 5:4 mux_pwgd<1:0> 00 r/w multiplexes various digital signals to the pwgd output pin 00: pwgd, powergood control signal 01: clk24m, 24mhz oszillator output 10: clkint2, internal clock signal, see clk_cntr regsiter 11: pwm, pmw_cntr register ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 71 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n 3:2 drive_xres<1:0> 00 r/w sets the xres output pin to open-drain, push-pull or tri-state and sets various driving strengths 00: 6ma open-drain output 01: 6ma push-pull output 10: 1ma push-pull output 11: hiz, stri-state 1:0 mux_xres<1:0> 00 r/w multiplexes various digital signals to the xres output pin 00: xres, active low reset signal 01: clk32k, 32khz rtc oszillator output 10: clkint1, internal clock signal, see clk_cntr regsiter 11: pwm, pmw_cntr register table 69. out_cntr2 register name base default out_cntr2 2-wire serial 00h offset: 1ah-2 q24m and q32k output control register this is an extended register and needs to be enabled by writing 010b to reg. 1ch first. this register is reset at a avdd27-por. bit bit name default access bit description 7:6 drive_q24m<1:0> 00 r/w sets the pwgd output pin to push-pull or tri-state and sets various driving strengths 00: 6ma push-pull output 01: hiz, stri-state 10: 2ma push-pull output 11: 1ma push-pull output 5:4 mux_q24m<1:0> 00 r/w multiplexes various digital signals to the pwgd output pin 00: clk24m, 24mhz oszillator output signal 01: clkint1, internal clock signal, see clk_cntr regsiter 10: clkint2, internal clock signal, see clk_cntr regsiter 11: pwm, pmw_cntr register 3:2 drive_q32k<1:0> 00 r/w sets the xres output pin to push-pull or tri-state and sets various driving strengths 00: 6ma push-pull output 01: hiz, stri-state 10: 2ma push-pull output 11: 1ma push-pull output 1:0 mux_q32k<1:0> 00 r/w multiplexes various digital signals to the xres output pin 00: clk32k, 32khz rtc oszillator output signal 01: clkint1, internal clock signal, see clk_cntr regsiter 10: clkint2, internal clock signal, see clk_cntr regsiter 11: pwm, pmw_cntr register table 68. out_cntr1 register name base default out_cntr1 2-wire serial 00h offset: 1ah-1 pwgd and xres output control register this is an extended register and needs to be enabled by writing 001b to reg. 1ch first. this register is reset at a avdd27-por. bit bit name default access bit description ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 72 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n table 70. out_cntr3 register name base default out_cntr3 2-wire serial 00h offset: 1ah-3 sdo and xirq output control register this is an extended register and needs to be enabled by writing 011b to reg. 1ch first. this register is reset at a avdd27-por. bit bit name default access bit description 7:6 drive_sdo<1:0> 00 r/w sets the sdo output pin to push-pull or tri-state and sets various driving strengths 00: 6ma push-pull output 01: hiz, stri-state 10: 2ma push-pull output 11: 1ma push-pull output 5:4 mux_sdo<1:0> 00 r/w multiplexes various digital signals to thesdo output pin 00: sdo, serial data output of the audio adc 01: clk24m, 24mhz oszillator output 10: clkint1, internal clock signal, see clk_cntr regsiter 11: pwm, pmw_cntr register 3:2 drive_xirq<1:0> 00 r/w sets the xirq output pin to open-drain, push-pull or tri-state and sets various driving strengths 00: 6ma open-drain output 01: 6ma push-pull output 10: 1ma push-pull output 11: hiz, stri-state 1:0 mux_xirq<1:0> 00 r/w multiplexes various digital signals to the xres output pin 00: xirq, active low interrupt request signal 01: clkint1, internal clock signal, see clk_cntr regsiter 10: clkint2, internal clock signal, see clk_cntr regsiter 11: irq, active low reset signal table 71. in_cntr register name base default in_cntr 2-wire serial 00h offset: 1ah-4 hbt and dimming input control register this is an extended register and needs to be enabled by writing 100b to reg. 1ch first. this register is reset at a avdd27-por. bit bit name default access bit description 7:4 - 0000 n/a 3:2 mux_hbt<1:0> 00 r/w selects the hbt (heartbeat) input pin 00: off, heartbeat input deactivated 01: pwgd pin 10: q24m pin 11: q32k pin 1:0 mux_extdim<1:0> 00 r/w selects the input pin for external dimming of the dcdc15 00: off, no pin selected in this mode the current sinks can be used without enabling the dcdc15. extdim_on bit has to be set in dcdc15 register. 01: pwgd pin 10: q24m pin 11: q32k pin ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 73 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n table 72. clk_cntr register name base default clk_cntr 2-wire serial 00h offset: 1ah-5 clock control register this is an extended register and needs to be enabled by writing 101b to reg. 1ch first. this register is reset at a avdd27-por. bit bit name default access bit description 7:6 clkint2<1:0> 00 r/w selects the clkint2 input source. note, this is an internal clock, which can be multiplexed to one of the gpio ouptus. 00: clkpll, internal pll clock 01: clklogdim, clock used for dimming the dcdc15 10: low, drives the signal to logic 0 11: high, drives the signal to logic 1 5:4 clkint1<1:0> 00 r/w selects the clkint1 frequency. note, this is an internal clock, which can be multiplexed to one of the gpio ouptus. 00: 2mhz 01: 887khz 10: 1khz 11: 125hz 3:2 clk24m<1:0> 00 r/w selects the clk24m frequency, clock of 24mhz oszillator 00: osc24mhz, oszillator frequency 01: osc24mhz_div2, oszillator frequency divided by 2 10: osc24mhz_div4, oszillator frequency divided by 4 11: osc24mhz_pd, osc24m is set to power down 1:0 clk32k<1:0> 00 r/w selects the clk32k frequnecy, clock of 32khz rtc oszillator 00: osc32khz, rtc oszillator frequency 01: 1hz 10: low, drives the signal to logic 0 11: high, drives the signal to logic 1 table 73. pwm_cntr register name base default pwm_cntr 2-wire serial 00h offset: 1ah-6 pwm control register this is an extended register and needs to be enabled by writing 110b to reg. 1ch first. this register is reset at a avdd27-por. bit bit name default access bit description 7 pwm_invert 0 r/w pwm output polarity 0: not inverted 1: inverted 6:0 pwm_cycle<6:0> 0000000 r/w sets the pwm duty cycle 0: no pulses 1-127: duty cycle = pwm_cycle * 0,39% ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 74 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n table 74. pll register name base default pll 2-wire serial 00h offset: 1ah-7 pll register this is an extended register and needs to be enabled by writing 111b to reg. 1ch first. this register is reset at a avdd27-por. bit bit name default access bit description 7:4 osr<3:0> 0000 r/w sets the oversampling rate when using the internal pll 0x0: 128 0x1-0xf: n/a 3:2 vco_mode<1:0> 00 r/w selects the speed of the pll vco according to the audio sampling frequency. 00: normal: 24-48khz 01: low: 8-23khz 10: high: 49-96khz 11: n/a 1:0 pll_mode<1:0> 00 r/w selects the pll mode and master clock frequency source 00: automatic turns pll on, pll clock is used as master clock if freq(lrck) >8khz and freq(mclk)<32*freq(lrck) 01: on; turns pll on, pll clock is used as master clock 10: off; turns the pll off, mclk is used as master clock 11: auto_inv; like automatic but with inverted clock table 75. dcdc15 register name base default dcdc15 2-wire serial 00h offset: 1bh-1 dcdc15 register this is an extended register and needs to be enabled by writing 001b to reg. 1ch first. this register is reset at a avdd27-por. bit bit name default access bit description 7 dim_up_xdown 0 r/w 0: disables the step-up converter and dims it down 1: enables the step-up converter and dims it up 6:5 dim_rate<1:0> 00 r/w selects the dimming speed when enabling or disablilng the dcdc15 00: 0ms 01: 300ms 10: 600ms 11: 1200ms 4 vfb_on 0 r/w 0: current feedback selected via isink1 and isink2 1: voltage feedback selected, isink1 is sinking 50ua to define the voltage via an external zener diode 3 extdim_on 0 r/w 0: selects internal clock for dimming 1: selects external clock for dimming 2:0 - 000 n/a ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 75 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n table 76. isink1 register name base default isink1 2-wire serial 00h offset: 1bh-2 isink1 register this is an extended register and needs to be enabled by writing 010b to reg. 1ch first. this register is reset at a avdd27-por. bit bit name default access bit description 7:3 i_sink1<4:0> 00000 r/w sets the current into current sink 1in 1.2ma steps 0: off, current sink 1 disabled 1-31 1.2ma * i_sink1 -> (1.2ma...37.2ma) 2:0 - 000 n/a table 77. isink2 register name base default isink2 2-wire serial 00h offset: 1bh-3 isink2 register this is an extended register and needs to be enabled by writing 011b to reg. 1ch first. this register is reset at a avdd27-por. bit bit name default access bit description 7:3 i_sink2<4:0> 00000 r/w sets the current into current sink 2in 1.2ma steps 0: off, current sink 2 disabled 1-31 1.2ma * i_sink2 -> (1.2ma...37.2ma) 2:0 - 000 n/a ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 76 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n table 78. pmu_enable register name base default pmu_enable 2-wire serial 00h offset: 1ch-2 pmu_enable register selects the extended register on address 17h to 1bh and enables writng to these pmu register. it also sets the adc10 multiplexer to measure various regulator voltages this register is reset at a avdd27-por. bit bit name default access bit description 7:4 dc_test_mux <3:0> 0000 r/w allows multiplexing internal and external supply voltages to one dc test node which can be further multiplexed to the adc10. the accuracy is 5mv/lsb (see reg. 2eh) 0x0: open 0x1: avdd27 0x2: avdd17 0x3: pvdd1 0x4: pvdd2 0x5: cvdd1 0x6: cvdd2 0x7: rvdd 0x8: fvdd 0x9: pwgd 0xa-0xf: n/a 3 pmu_gate 000 r/w enables all settings made in registers 17h to 1bh at once. if this bit is set, changes are activated as soon as they are written to the related register. 0: no change 1: change at once 2:0 pmu_wr_enable <2:0> 000 r/w selects extended registers 17h to 1bh for the next write 0: no register selected 1: 17h-1 to 1bh-1 selected 2: 17h-2 to 1bh-2 selected ... 7: 17h-7 to 1bh-7 selected ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 77 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n table 79. system register name base default system 2-wire serial 41h offset: 20h system register this register is reset at a avdd27-por. bit bit name default access bit description 7:4 design_version<3:0> 0100 r afe number to identify the design version 0100: for chip version 3v0 3 hb_wd_on 0 r/w heartbeat (hbt) watchdog the watchdog counter will be reset by a rising edge at the hbt input pin which has to occur at least every 500ms. if the watchdog counter is not reset, the afe will be powered down. 0: hbt watchdog is disabled 1: hbt watchdog is enabled 2 jtemp_off 0 r/w junction temperature supervision (level can be set in register 21h) 0: temperature supervision enabled 1: temperature supervision disabled 1 i2c_wd_on 0 r/w 2-wire serial interface watchdog to reset the watchdog counter a 2-wire serial read operation has to be performed at least every 500ms. if the watchdog counter is not reset, the afe will be powered down. 0: watchdog is disabled 1: watchdog is enabled 0 pwr_hold 0 r/w 0: power up hold is cleared and afe will power down 1: is automatically set to on after power on table 80. supervisor register name base default supervisor 2-wire serial 00h offset: 21h supervisor register this register is reset at a avdd27-por. bit bit name default access bit description 7 sd_time 0100 r/w sets the emergency shut-down time invoked by pwrup. 0: 5.4sec 1: 10.9sec 6 bvddlow_sd_off 0 r/w 0: bvddlow shut down enalbed 1: bvddlow shut down disabled 5 - 0 n/a 4:0 jtemp_sup<4:0> 0 r/w sets the threshold for junction temperature emergency shutdown and junction temperature interrupt invoke shutdown at: jtemp_sd=140-jtemp_sup*5 c invoke interrupt at: jtemp_irq=120-jtemp_sup*5 c ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 78 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n table 81. ram & wakeup register name base default ram & wakeup 2-wire serial 00h offset: 22h ram & wakeup register sets and enables the rtc wake-up counter and programs the 128bit sram. 3 bytes need to be written in a sequence to set the counter. the msb of the 3 rd byte enables the wake-up counter. byte 4 19 will program the static 128bit sram which is supplied by rvdd. this register keeps its content during normal shut-down and is only reset at a rvdd-por. bit byte name default access bit description 7:0 wake_up_byte_0 (1 st write to 0x19 is byte 0) 00h r/w 0000 0001b: 1sec 0000 0010b: 2sec 0000 0100b: 4sec 0000 1000b: 8sec 0001 0000b: 16sec 0010 0000b: 32sec 0100 0000b: 64sec 1000 0000b: 128sec 7:0 wake_up_byte_1 (2 nd write to 0x19 is byte 1) 00h r/w 0000 0001b: 256sec 0000 0010b: 512sec 0000 0100b: 1 024sec 0000 1000b: 2 048sec 0001 0000b: 4 096sec 0010 0000b: 8 192sec 0100 0000b: 16 384sec 1000 0000b: 32 768sec 7:0 wake_up_byte_2 (3 rd write to 0x19 is byte 2) 00h n/a 000 0001b: 65 536sec 000 0010b: 131 072sec 000 0100b: 262 144sec 000 1000b: 524 288sec 001 0000b: 1 048 576sec 010 0000b: 2 097 152sec 100 0000b: 4 194 304sec 0xxx xxxxxb = wake-up disabled 1xxx xxxxxb = wake-up enabled 7:0 sram_128<0:15> (4 th 19 th write to 0x22 programs the 128bit static sram) 00h r/w xxxx xxxxb = byte 0 : xxxx xxxxb = byte 15 ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 79 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n table 82. first interrupt register name base default irqenrd_0 2-wire serial 00h offset: 23h first interrupt register please be aware that writing to this register will enable/disable the corresponding interrupts, while reading gets the actual interrupt status and will clear the register at the same time. it is not possible to read back the interrupt enable/disable settings. this register is reset at a avdd27-por. bit bit name default access bit description 7 cvdd1_sd 0 w invokes shut-down of afe when a C10% under-voltage spike at cvdd1 occurs 0: disable 1: enable cvdd1_under x r this bit is set when a C5% under-voltage at cvdd1 occurs 6 cvdd1_irq 0 w enables interrupt for over-voltage/under-voltage supervision of cvdd1 0: disable 1: enable cvdd1_over x r this bit is set when a +8% over-voltage at cvdd1 occurs 5:4 - 00 n/a 3 pvdd2_sd 0 w invokes shut-down of afe when a C10% under-voltage spike at pvdd2 occurs 0: disable 1: enable pvdd2_under x r this bit is set when a C5% under-voltage at pvdd2 occurs 2 pvdd2_irq 0 w enables interrupt for over-voltage/under-voltage supervision of pvdd2 0: disable 1: enable pvdd2_over x r this bit is set when a +5% over-voltage at pvdd2 occurs 1 pvdd1_sd 0 w invokes shut-down of afe when a C10% under-voltage spike at pvdd1 occurs 0: disable 1: enable pvdd1_under x r this bit is set when a C5% under-voltage at pvdd1 occurs 0 pvdd1_irq 0 w enables interrupt for over-voltage/under-voltage supervision of pvdd1 0: disable 1: enable pvdd1_over x r this bit is set when a +5% over-voltage at pvdd1 occurs ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 80 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n table 83. second interrupt register name base default irqenrd_1 2-wire serial 00h offset: 24h second interrupt register please be aware that writing to this register will enable/disable the corresponding interrupts, while reading gets the actual interrupt status and will clear the register at the same time. it is not possible to read back the interrupt enable/disable settings. this register is reset at a avdd27-por. bit bit name default access bit description 7 pwrup_irq 0 w enables interrupt which is invoked whenever a high signal at the pwrup input pin occurs 0: disable 1: enable x r this bit is set whenever a high level of min. bvdd/3 at the pwrup input pin occurs (pwrup pin is commonly connected to the power-up button) 6 wakeup_irq 0 w enables interrupt which is invoked whenever a wake-up from rtc wake-up counter occurs 0: disable 1: enable x r this bit is set when a wake-up has been invoked by the rtc wake-up counter. 5 mclk_irq 0 w enables interrupt which is invoked whenever a high signal at the mclk input pin occurs 0: disable 1: enable x r this bit is set whenever a high level of min. bvdd/3 at the mclk input pin occurs (mclk pin can be used as alternative power-up button) 4:2 - 0 n/a 1 cvdd2_sd 0 w invokes shut-down of afe when a C10% under-voltage spike at cvdd2 occurs 0: disable 1: enable cvdd2_under x r this bit is set when a C5% under-voltage at cvdd2 occurs 0 cvdd2_irq 0 w enables interrupt for over-voltage/under-voltage supervision of cvdd2 0: disable 1: enable cvdd2_over x r this bit is set when a +8% over-voltage at cvdd2 occurs ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 81 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n table 84. thrid interrupt register name base default irqenrd_2 2-wire serial 00h offset: 25h third interrupt register please be aware that writing to this register will enable/disable the corresponding interrupts, while reading gets the actual interrupt status and will clear the register at the same time. it is not possible to read back the interrupt enable/disable settings. this register is reset at a avdd27-por. bit bit name default access bit description 7 battemp_irq 0 w battery over-temperature interrupt setting. 0: disable 1: enable interrupt if battery temperature exceeds 45/55c the interrupt must not be enabled if the charger block and battery temperature supervision is disabled x r battery over-temperature interrupt reading 0: battery temperature below 45/55c 1: battery temperature was too high and the charger was turned off. the charger will be turned on again, when the temperature gets below 42/50c 6 chg_eoc x r battery end of charge interrupt reading 0: battery charging in progress 1: charging is complete, charging current is below 10% of nominal current, turn off charger 5 chg_con x r 0: no charger input source connected 1: charger input source connected, also valid if charger is connected during wakeup 4 chg_irq 0 w charger status change interrupt setting 0: disable 1: enables an interrupt on a low to high or high to low change of chgin pin or on an eoc condition chg_changed (status change) x r charger input status change interrupt reading 0: charger status not changed 1: charger status changed, check chg_con, chg_eoc 3 usb_con 0 n/a 0: no usb input connected 1: usb input connected, also valid if usb is connected during wakeup. the threshold can be set in the usb_util register (1ah) 2 usb_irq 0 w usb input status change interrupt setting 0: disable 1: enables an interrupt on a low to high or high to low change of vbus pin. the threshold can be set in the usb_util register (1ah) usb_changed (status change) x r usb input status change interrupt reading 0: usb input status not changed 1: usb input status changed, check usb_con ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 82 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n 1 rtc_wd (level) 0 w real time clock watchdog interrupt setting 0: disable 1: enable x r real time clock watchdog interrupt reading 0: rtc o.k. 1: rtc oszillator was stopped, rtc not longer valid the interrupt gets set in hibernation or during power-up even if the interrupt is not enabled thus allowing to recognise a change of the battery connected to bvddr during hibernation or shutdown. for a valid reading, the interrupt has to be enabled first. 0 bvdd_low (level) 0 w bvdd under-voltage supervisor interrupt setting 0: disable 1: enable x r bvdd supervisor interrupt reading 0: bvdd is above brown out level 1: bvdd has reached brown out level the threshold can be set in the supervisor register (21h) table 85. fourth interrupt register name base default irqenrd_3 2-wire serial 00h offset: 26h fourth interrupt register please be aware that writing to this register will enable/disable the corresponding interrupts, while reading gets the actual interrupt status and will clear the register at the same time. it is not possible to read back the interrupt enable/disable settings. this register is reset at a avdd27-por. bit bit name default access bit description 7 jtemp_high (level) 0 w supervisor junction over-temperature interrupt setting 0: disable 1: enable x r supervisor junction over-temperature interrupt reading 0: chip temperature below threshold 1: chip temperature has reached the threshold the threshold can be set in the supervisor register (21h) 6 - 0 n/a table 84. thrid interrupt register name base default irqenrd_2 2-wire serial 00h offset: 25h third interrupt register please be aware that writing to this register will enable/disable the corresponding interrupts, while reading gets the actual interrupt status and will clear the register at the same time. it is not possible to read back the interrupt enable/disable settings. this register is reset at a avdd27-por. bit bit name default access bit description ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 83 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n 5 hp_ovc (level) 0 w headphone over-current interrupt setting 0: disable 1: enable the interrupt must not be enabled if the headphone block is disabled x r headphone over-current interrupt reading 0: no over-current detected 1: headphone over-current detected, headphone amplifier was shut down. the current thresholds are 150ma at hpr / hpl pin or 300ma at hpcm pin. 4 i2s_status x r 0: no lrck on i2s interface detected 1: lrck on i2s interface present 3 i2s_irq 0 w i2s input status change interrupt setting 0: disable 1: enable i2s_changed (status change) x r i2s input status change interrupt reading 0: i2s input status not changed 1: i2s input status changed, check i2s_status 2 voxm_irq 0 w enables interrupt which is invoked by reaching a voltage threshold at the mic input (voice activation) 0: disable 1: enable x r this bit is set when a voltage threshold of 5mv rms (unfiltered) at the mic has been reached (voice activation) 1 mic_con (level) 0 w microphone connect detection interrupt setting 0: disable 1: enable x r microphone connect detection interrupt reading 0: no microphone connected to mic input 1: microphone connected at mic input. this interrupt is only invoked when the microphone stage is powered down. the irq will be released after enabling the microphone stage. detecting a microphone during operation has to be done by measuring the supply current 0 hph_con (level) 0 w headphone connect detection interrupt setting 0: disable 1: enable x r headphone connect detection interrupt reading 0: no headphone connected 1: headphone connected this interrupt is only invoked when the headphone stage is powered down. the irq will be released after enabling the headphone stage. detecting a headphone during operation is not possible. table 85. fourth interrupt register name base default irqenrd_3 2-wire serial 00h offset: 26h fourth interrupt register please be aware that writing to this register will enable/disable the corresponding interrupts, while reading gets the actual interrupt status and will clear the register at the same time. it is not possible to read back the interrupt enable/disable settings. this register is reset at a avdd27-por. bit bit name default access bit description ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 84 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n table 86. fifth interrupt register name base default irqenrd_4 2-wire serial 00h offset: 27h fifth interrupt register please be aware that writing to this register will enable/disable the corresponding interrupts, while reading gets the actual interrupt status and will clear the register at the same time. it is not possible to read back the interrupt enable/disable settings. this register is reset at a avdd27-por. bit bit name default access bit description 7:6 t_deb<1:0> 00 r/w sets the usb and charger connect de-bounce time: 00: 512ms 01: 256ms 10: 128ms 11: 0ms 5 avdd27_irq 0 w enables interrupt for under-voltage supervision of avdd27 0: disable 1: enable avdd27_under x r this bit is set when a -5% under-voltage at avdd27 occurs 4 dcdc15_irq 0 w enables interrupt for over-voltage supervision of sw15 0: disable 1: enable dcdc15_over x r this bit is set when sw15 exceeds 15v. 3 - 0 n/a 2 rem_det (edge) 0 w microphone remote key press detection interrupt setting 0: disable 1: enable x r microphone remote key press detection interrupt reading 0: no key press detected 1: microphone supply current got increased, remote key press detected -> measure mics supply current 1 rtc_update (edge) 0 w rtc timer interrupt setting 0: disable 1: enable x r rtc timer interrupt reading 0: no rtc interrupt occurred 1: rtc timer interrupt occurred. selecting minute or second interrupt can be done via rtct register (29h) 0 adc_eoc (edge) 0 w adc end of conversion interrupt setting 0: disable 1: enable x r adc end of conversion interrupt reading 0: adc conversion not finished 1: adc conversion finished. read out adc_0 and adc_1 register to get the result (2eh & 2fh) ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 85 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n table 87. rtc_cntr register name base default rtc_cntr 2-wire serial 03h offset: 28h rtc control register this register is reset at a rvdd-por. bit bit name default access bit description 7:4 free_bits<3:0> 0000 r/w free bits to be used for application purpose 3:2 - 00 n/a 1 rtc_on 1 r/w rtc counter clock control: 0: disable clock for rtc counter 1: enables clock for rtc counter 0 osc_on 1 rw rtc oscillator control: 0: disable rtc oscillator 1: enable rtc oscillator table 88. rtc_time register name base default rtc_time 2-wire serial 03h offset: 29h rtc timing register this register is reset at a rvdd-por. bit bit name default access bit description 7 irq_min 0 r/w 0: generates an interrupt every second 1: generates an interrupt every minute the interrupt has to be enable in irqenrd_4 (27h) 6:0 trtc<6:0> 1000000 r/w these bits are used to correct the inaccuracy of the used 32khz crystal. trimming register for rtc, 128 steps @ 7.6ppm 000000: 1 (7.6ppm) 000001: 2 (15.2ppm) 100000: 64 (488ppm) 111110: 126 (960.8ppm) 111111: 127 (968.4ppm) table 89. rtc_0 to rtc_3 register name base default rtc_0 to rtc_3 2-wire serial 03h offset: 2ah to 2dh rtc counter seconds register this register is reset at a rvdd-por. adr. byte name default access bit description 2ah rtc_0 00h r/w qrtc<7:0>; rtc seconds bits 0 to 7 2bh rtc_1 00h r/w qrtc<15:8>; rtc seconds bits 8 to 15 2ch rtc_2 00h r/w qrtc<23:9>; rtc seconds bits 9 to 23 2dh rtc_3 00h r/w qrtc<31:24>; rtc seconds bits 24 to 31 ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 86 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n table 90. adc10_0 register name base default adc10_0 2-wire serial 0000 00xxb offset: 2eh first 10-bit adc register writing to this register will start the measurement of the selected source. this register is reset at a avdd27-por, exception are bit 0 and 1 bit bit name default access bit description 7:4 adc10_mux<3:0> 0000 r/w selects adc input source 0000: bvdd 0001: bvddr 0010: chgin 0011: chgout 0100: vbus 0101: defined by dc_test in register 0x1c 0110: battemp 0111: reserved 1000: mics 1001: reserved 1010: i_mics 1011: reserved 1100: vbe_1ua 1101: vbe_2ua 1110: i_chgact 1101: i_chgref 3:2 - 00 n/a 1:0 adc10<9:8> xx r adc result bit 9 to 8 table 91. adc10_1 register name base default adc10_1 2-wire serial xxh offset: 2fh second 10-bit adc register this register is reset at a avdd27-por. bit bit name default access bit description 7:0 adc10<7:0> 00h r adc results bits 7 to 0 ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 87 - 91 AS3543 3v2 data sheet - r e g i s t e r d e f i n i t i o n table 92. uid_0 to uid_7 register name base default uid_0 to uid7 2-wire serial n/a offset: 38h to 3fh unique id register this is a read only register and gets not reset. adr. byte name default access bit description 38h uid_0 n/a r unique id byte 0 39h uid_1 n/a r unique id byte 1 3ah uid_2 n/a r unique id byte 2 3bh uid_3 n/a r unique id byte 3 3ch uid_4 n/a r unique id byte 4 3dh uid_5 n/a r unique id byte 5 3eh uid_6 n/a r unique id byte 6 3fh uid_7 n/a r unique id byte 7 ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 88 - 91 AS3543 3v2 data sheet - a p p l i c a t i o n i n f o r m a t i o n 12 application information figure 30. typical application schematic 5 5 4 4 3 3 2 2 1 1 d d c c b b a a battery battemp usb 5v dc 5v two wire interface data two wire interface clock AS3543 interrupt i2s lrck i2s sclk i2s sdi cpu reset# i2s sdo usb backlight cathode backlight anode line out right line out left line input right line input left avdd27 bvdd bvdd bvdd dvdd dvdd bvdd bvdd iovdd / 3.3v vddcore / 1.2v vddmem / 1.8v bvdd vddmem / 1.8v iovdd / 3.3v vddmem / 1.8v r10 10k r10 10k d9 d9 c7 2.2uf c7 2.2uf y1 32khz y1 32khz d8 d8 r3 47k r3 47k c21 10uf c21 10uf c25 10uf c25 10uf r2 47k r2 47k c24 470nf c24 470nf l3 4.7uh l3 4.7uh c11 2.2uf c11 2.2uf r1 47k r1 47k c4 100nf c4 100nf u2 headphone output u2 headphone output l 3 gnd 1 r 2 c3 100uf c3 100uf d7 d7 i2c int. i2s interface start - up sequence dcdc buck converter 15vdcdc bl-booster prg ldos system supply charger digital supply digital filter rtc audio supplies audio inputs audio outputs power up reset out AS3543 24mhz output u1 AS3543 i2c int. i2s interface start - up sequence dcdc buck converter 15vdcdc bl-booster prg ldos system supply charger digital supply digital filter rtc audio supplies audio inputs audio outputs power up reset out AS3543 24mhz output u1 AS3543 dvss k5 dvdd k6 fvdd g2 avdd17in b5 avdd17 h10 avdd27 h9 bvdd b4 bvddp1 b3 pvdd1 a3 pvdd2 a5 cvdd1 h2 cvss12 h1 lxc1 j1 bvddc1 k1 cvdd2 f2 lxc2 f1 bvddc2 e1 sw15v c2 vss15v c1 isink1 e2 isink2 d2 battemp b2 chgin b1 chgout a1 vbus d5 csda k8 cscl j8 sdi g5 sdo g6 sclk f4 lrck g4 pwgd j5 xres j3 xirq j4 pwrup j2 vprog1 g7 lin1r c9 lin1l c10 lin2r d6 lin2l d7 micp e10 micn e9 mics d9 loutr b9 loutl b10 lognd b8 hpr a8 hpl a10 hpgnd b6 hpcm a6 hpvdd b7 hpvss a9 vref g9 agnd f9 avss f10 bvddr k9 rvdd j9 xin32k j10 xout32k k10 q32k j7 vprog2 f7 vprog3 e7 xin24m k2 xout24m k3 q24m j6 bvddbsw a2 mclk e4 vss d4 s1 power up s1 power up 1 2 c9 10uf c9 10uf c19 3.3uf c19 3.3uf c10 10uf c10 10uf c5 2.2uf c5 2.2uf c16 10uf c16 10uf c23 470nf c23 470nf r8 47k r8 47k r7 1k r7 1k d2 d2 c1 100uf - 220uf c1 100uf - 220uf r9 47k r9 47k r6 1k r6 1k r5 100r r5 100r c20 10uf c20 10uf c2 100uf - 220uf c2 100uf - 220uf c15 100nf c15 100nf d3 d3 c29 33nf c29 33nf d1 d1 c12 100nf c12 100nf d4 d4 l1 22uh l1 22uh c14 1uf c14 1uf c13 22nf c13 22nf c17 220nf c17 220nf c28 2.2uf c28 2.2uf mic1 microphone mic1 microphone 1 2 c26 10uf c26 10uf c27 2.2uf c27 2.2uf c18 220nf c18 220nf r4 47k r4 47k c6 2.2uf c6 2.2uf u3 li-ion battery u3 li-ion battery . . d5 d5 l2 4.7uh l2 4.7uh c22 3.3uf c22 3.3uf c8 47nf c8 47nf d6 d6 r11 10k r11 10k ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 89 - 91 AS3543 3v2 data sheet - p a c k a g e d r a w i n g s a n d m a r k i n g s 13 package drawings and markings figure 31. ctbga67 marking figure 32. ctbga68 6x6 0.5mm pitch table 93. package code aywwzzz a y ww zzz b ... for green year working week assembly / packaging free choice ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 90 - 91 AS3543 3v2 data sheet - o r d e r i n g i n f o r m a t i o n 14 ordering information note: e temperature range: -20oc - 85oc ct package: ctbga p delivery form: tape & reel dry pack table 94. ordering information model description delivery form package AS3543-ectp high end stereo audio codec with system pmu tape & reel dry pack 68-ball ctbga 0.5mm pitch (6.0mm x 6.0mm) ams ag technical content still valid
www.austriamicrosystems.com revision 1.11 91 - 91 AS3543 3v2 data sheet - o r d e r i n g i n f o r m a t i o n copyrights copyright ? 1997-2011, austriamicrosystems ag, schloss premstaetten, 8141 unterpremstaetten, austria-europe. trademarks registered ?. all rights reserved. the material herein may not be reproduced, adapted, merged, trans- lated, stored, or used without the prior written consent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by austriamicrosystems ag are covered by the warranty and patent indemnification provisions appearing in its term of sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriami- crosystems ag reserves the right to change specifications and prices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life- sustaining equipment are specifically not recommended without additional processing by austriamicrosystems ag for each application. for shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. the information furnished here by austriamicrosystems ag is believed to be correct and accurate. however, austriamicrosystems ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the tech- nical data herein. no obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services. contact information headquarters austriamicrosystems ag a-8141 schloss premstaetten, austria tel: +43 (0) 3136 500 0 fax: +43 (0) 3136 525 01 for sales offices, distributors and representatives, please visit: http://www.austriamicrosystems.com/contact ams ag technical content still valid

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